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MIPS: Add MSI support for XLP9XX

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In XLP9XX, the interrupt routing table for MSI-X has been moved to the
PCIe controller's config space from PIC. There are also 32 MSI-X
interrupts available per link on XLP9XX.

Update XLP MSI/MSI-X code to handle this.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: g@linux-mips.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6912/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam 2014-05-09 16:35:49 +05:30 • committed by Ralf Baechle
parent 1c98398662
commit d66f3f0e10
4 changed files with 156 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

14
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
View file

@ -69,6 +69,20 @@
#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264
#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
#define PCIE_9XX_MSI_STATUS 0x283
#define PCIE_9XX_MSI_EN 0x284
/* 128 MSIX vectors available in 9xx */
#define PCIE_9XX_MSIX_STATUS0 0x286
#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286)
#define PCIE_9XX_MSIX_VEC 0x296
#define PCIE_9XX_MSIX_VECX(n) (n + 0x296)
#define PCIE_9XX_INT_STATUS0 0x397
#define PCIE_9XX_INT_STATUS1 0x398
#define PCIE_9XX_INT_EN0 0x399
#define PCIE_9XX_INT_EN1 0x39a
/* other */
#define PCIE_NLINKS 4

4
arch/mips/include/asm/netlogic/xlp-hal/pic.h
View file

@ -199,6 +199,10 @@
#define PIC_IRT_PCIE_LINK_3_INDEX 81
#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191
#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
#define PIC_CLOCK_TIMER 7
#if !defined(LOCORE) && !defined(__ASSEMBLY__)

5
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
View file

@ -70,8 +70,9 @@
#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */
#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */
#define NLM_PIC_INDIRECT_VEC_BASE 512
#define NLM_GPIO_VEC_BASE 768