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drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_20v2.c

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Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:110:6-13: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:113:2-9: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:243:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:244:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:267:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:268:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:272:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:273:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:283:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:285:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:673:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:962:1-9: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
zhengbin 2019-12-24 11:27:42 +08:00 • committed by Alex Deucher
parent b7402f1f6b
commit d94af04b08
1 changed files with 12 additions and 12 deletions
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24
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
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@ -107,10 +107,10 @@ static unsigned int get_bytes_per_element(enum source_format_class source_format
static bool is_dual_plane(enum source_format_class source_format) static bool is_dual_plane(enum source_format_class source_format)
{ {
bool ret_val = 0; bool ret_val = false;
if ((source_format == dm_420_8) || (source_format == dm_420_10)) if ((source_format == dm_420_8) || (source_format == dm_420_10))
ret_val = 1; ret_val = true;
return ret_val; return ret_val;
} }
@ -240,8 +240,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib,
unsigned int swath_bytes_c = 0; unsigned int swath_bytes_c = 0;
unsigned int full_swath_bytes_packed_l = 0; unsigned int full_swath_bytes_packed_l = 0;
unsigned int full_swath_bytes_packed_c = 0; unsigned int full_swath_bytes_packed_c = 0;
bool req128_l = 0; bool req128_l = false;
bool req128_c = 0; bool req128_c = false;
bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
bool surf_vert = (pipe_src_param.source_scan == dm_vert); bool surf_vert = (pipe_src_param.source_scan == dm_vert);
unsigned int log2_swath_height_l = 0; unsigned int log2_swath_height_l = 0;
@ -264,13 +264,13 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib,
total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
req128_l = 0; req128_l = false;
req128_c = 0; req128_c = false;
swath_bytes_l = full_swath_bytes_packed_l; swath_bytes_l = full_swath_bytes_packed_l;
swath_bytes_c = full_swath_bytes_packed_c; swath_bytes_c = full_swath_bytes_packed_c;
} else { //128b request (for luma only for yuv420 8bpc) } else { //128b request (for luma only for yuv420 8bpc)
req128_l = 1; req128_l = true;
req128_c = 0; req128_c = false;
swath_bytes_l = full_swath_bytes_packed_l / 2; swath_bytes_l = full_swath_bytes_packed_l / 2;
swath_bytes_c = full_swath_bytes_packed_c; swath_bytes_c = full_swath_bytes_packed_c;
} }
@ -280,9 +280,9 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib,
total_swath_bytes = 2 * full_swath_bytes_packed_l; total_swath_bytes = 2 * full_swath_bytes_packed_l;
if (total_swath_bytes <= detile_buf_size_in_bytes) if (total_swath_bytes <= detile_buf_size_in_bytes)
req128_l = 0; req128_l = false;
else else
req128_l = 1; req128_l = true;
swath_bytes_l = total_swath_bytes; swath_bytes_l = total_swath_bytes;
swath_bytes_c = 0; swath_bytes_c = 0;
@ -670,7 +670,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
const display_pipe_source_params_st pipe_src_param, const display_pipe_source_params_st pipe_src_param,
bool is_chroma) bool is_chroma)
{ {
bool mode_422 = 0; bool mode_422 = false;
unsigned int vp_width = 0; unsigned int vp_width = 0;
unsigned int vp_height = 0; unsigned int vp_height = 0;
unsigned int data_pitch = 0; unsigned int data_pitch = 0;
@ -959,7 +959,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
// Source // Source
// dcc_en = src.dcc; // dcc_en = src.dcc;
dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
mode_422 = 0; // TODO mode_422 = false; // TODO
access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
// bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
// bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);