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PCI: tegra194: Fix possible array out of bounds access
[ Upstream commit 205b3d02d5
]
Add check to fix the possible array out of bounds violation by
making speed equal to GEN1_CORE_CLK_FREQ when its value is more
than the size of "pcie_gen_freq" array. This array has size of
four but possible speed (CLS) values are from "0 to 0xF". So,
"speed - 1" values are "-1 to 0xE".
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/
Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
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commit
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1 changed files with 11 additions and 2 deletions
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@ -239,6 +239,7 @@
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#define EP_STATE_ENABLED 1
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static const unsigned int pcie_gen_freq[] = {
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GEN1_CORE_CLK_FREQ, /* PCI_EXP_LNKSTA_CLS == 0; undefined */
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GEN1_CORE_CLK_FREQ,
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GEN2_CORE_CLK_FREQ,
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GEN3_CORE_CLK_FREQ,
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@ -452,7 +453,11 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
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speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
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PCI_EXP_LNKSTA_CLS;
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clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
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if (speed >= ARRAY_SIZE(pcie_gen_freq))
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speed = 0;
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clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
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/* If EP doesn't advertise L1SS, just return */
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val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
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@ -989,7 +994,11 @@ retry_link:
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speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
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PCI_EXP_LNKSTA_CLS;
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clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
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if (speed >= ARRAY_SIZE(pcie_gen_freq))
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speed = 0;
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clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
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tegra_pcie_enable_interrupts(pp);
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