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x86, cacheinfo: Fix disabling of L3 cache indices

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* Correct the masks used for writing the cache index disable indices.
* Do not turn off L3 scrubber - it is not necessary.
* Make sure wbinvd is executed on the same node where the L3 is.
* Check for out-of-bounds values written to the registers.
* Make show_cache_disable hex values unambiguous
* Check for Erratum #388

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1264172467-25155-4-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Borislav Petkov 2010-01-22 16:01:05 +01:00 • committed by H. Peter Anvin
parent 48a719c238
commit dcf39daf3d
1 changed files with 21 additions and 13 deletions
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34
arch/x86/kernel/cpu/intel_cacheinfo.c
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@ -18,6 +18,7 @@
#include <asm/processor.h> #include <asm/processor.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <asm/k8.h> #include <asm/k8.h>
#include <asm/smp.h>
#define LVL_1_INST 1 #define LVL_1_INST 1
#define LVL_1_DATA 2 #define LVL_1_DATA 2
@ -299,8 +300,10 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
if (boot_cpu_data.x86 == 0x11) if (boot_cpu_data.x86 == 0x11)
return; return;
/* see erratum #382 */ /* see errata #382 and #388 */
if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8)) if ((boot_cpu_data.x86 == 0x10) &&
((boot_cpu_data.x86_model < 0x9) ||
(boot_cpu_data.x86_mask < 0x1)))
return; return;
this_leaf->can_disable = 1; this_leaf->can_disable = 1;
@ -726,12 +729,12 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
return -EINVAL; return -EINVAL;
pci_read_config_dword(dev, 0x1BC + index * 4, &reg); pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
return sprintf(buf, "%x\n", reg); return sprintf(buf, "0x%08x\n", reg);
} }
#define SHOW_CACHE_DISABLE(index) \ #define SHOW_CACHE_DISABLE(index) \
static ssize_t \ static ssize_t \
show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \ show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
{ \ { \
return show_cache_disable(this_leaf, buf, index); \ return show_cache_disable(this_leaf, buf, index); \
} }
@ -745,7 +748,9 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
int node = cpu_to_node(cpu); int node = cpu_to_node(cpu);
struct pci_dev *dev = node_to_k8_nb_misc(node); struct pci_dev *dev = node_to_k8_nb_misc(node);
unsigned long val = 0; unsigned long val = 0;
unsigned int scrubber = 0;
#define SUBCACHE_MASK (3UL << 20)
#define SUBCACHE_INDEX 0xfff
if (!this_leaf->can_disable) if (!this_leaf->can_disable)
return -EINVAL; return -EINVAL;
@ -759,21 +764,24 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
if (strict_strtoul(buf, 10, &val) < 0) if (strict_strtoul(buf, 10, &val) < 0)
return -EINVAL; return -EINVAL;
val |= 0xc0000000; /* do not allow writes outside of allowed bits */
if (val & ~(SUBCACHE_MASK | SUBCACHE_INDEX))
return -EINVAL;
pci_read_config_dword(dev, 0x58, &scrubber); val |= BIT(30);
scrubber &= ~0x1f000000;
pci_write_config_dword(dev, 0x58, scrubber);
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val); pci_write_config_dword(dev, 0x1BC + index * 4, val);
/*
* We need to WBINVD on a core on the node containing the L3 cache which
* indices we disable therefore a simple wbinvd() is not sufficient.
*/
wbinvd_on_cpu(cpu);
pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
return count; return count;
} }
#define STORE_CACHE_DISABLE(index) \ #define STORE_CACHE_DISABLE(index) \
static ssize_t \ static ssize_t \
store_cache_disable_##index(struct _cpuid4_info *this_leaf, \ store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
const char *buf, size_t count) \ const char *buf, size_t count) \
{ \ { \
return store_cache_disable(this_leaf, buf, count, index); \ return store_cache_disable(this_leaf, buf, count, index); \