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Merge branch 'CR_1314_DRM_INNO_Screen_compatibility_Keith.zhao' into 'jh7110-5.15.y-devel'

Browse source 
Cr 1314 drm inno screen compatibility keith.zhao

See merge request sdk/linux!357
This commit is contained in:
Jason Zhou 2022-08-05 09:38:10 +00:00
commit df2e5af47e
2 changed files with 17 additions and 23 deletions
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22
drivers/gpu/drm/i2c/tda998x_drv.c
View file

@ -1392,6 +1392,12 @@ static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
return MODE_BAD_HVALUE;
if (mode->vtotal >= BIT(11))
return MODE_BAD_VVALUE;
//u32 vic = drm_match_cea_mode(mode);
//if (vic >= 1)
// return MODE_OK;
//else
// return MODE_BAD;
return MODE_OK;
}
@ -1599,12 +1605,16 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
* TDA19988 requires high-active sync at input stage,
* so invert low-active sync provided by master encoder here
*/
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
reg |= VIP_CNTRL_3_H_TGL;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
reg |= VIP_CNTRL_3_V_TGL;
reg_write(priv, REG_VIP_CNTRL_3, reg);
printk("REG_VIP_CNTRL_3 = %02x\n",reg);
//reg_write(priv, REG_VIP_CNTRL_3, 0x26);
//reg_write(priv, REG_VIDFORMAT, 0x06);
reg_write(priv, REG_VIDFORMAT, 0x00);
reg_write16(priv, REG_REFPIX_MSB, ref_pix);
reg_write16(priv, REG_REFLINE_MSB, ref_line);
@ -1637,11 +1647,13 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
* revert input stage toggled sync at output stage
*/
reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
reg |= TBG_CNTRL_1_H_TGL;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
reg |= TBG_CNTRL_1_V_TGL;
reg_write(priv, REG_TBG_CNTRL_1, reg);
printk("REG_TBG_CNTRL_1 = %02x\n",reg);
//reg_write(priv, REG_TBG_CNTRL_1, 0x46);
/* must be last register set: */
reg_write(priv, REG_TBG_CNTRL_0, 0);

18
drivers/gpu/drm/verisilicon/inno_hdmi.c
View file

@ -137,7 +137,6 @@ static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
{
printk("write: addr 0x%02x, val 0x%02x\n",offset,val);
writel_relaxed(val, hdmi->regs + (offset) * 0x04);
}
@ -533,8 +532,6 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi,
val = readl_relaxed(hdmi->regs + (0x1b0) * 0x04);
val |= 0x4;
//writel_relaxed(val, hdmi->regs + (0x1b0) * 0x04);
//writel_relaxed(0xf, hdmi->regs + (0x1cc) * 0x04);
hdmi_writeb(hdmi, 0x1b0, val);
hdmi_writeb(hdmi, 0x1cc, 0xf);
hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
@ -553,14 +550,8 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi,
hdmi_writeb(hdmi, 0x1be, 0x70);
inno_hdmi_tx_phy_power_down(hdmi);
hdmi_writeb(hdmi, 0xC9, 0x40);
inno_hdmi_tx_ctrl(hdmi);
//hdmi_writeb(hdmi, 0x100, 0x02);
//drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, true);
//drm_scdc_set_scrambling(hdmi->ddc, true);
hdmi_writeb(hdmi, 0x35, 0x01);
hdmi_writeb(hdmi, 0x38, 0x04);
hdmi_writeb(hdmi, 0x40, 0x18);
@ -621,11 +612,6 @@ inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
//struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
//s->output_mode = ROCKCHIP_OUT_MODE_P888;
//s->output_type = DRM_MODE_CONNECTOR_HDMIA;
return 0;
}
@ -773,10 +759,6 @@ inno_hdmi_connector_mode_valid(struct drm_connector *connector,
return (valid) ? MODE_OK : MODE_BAD;
#endif
u32 vic = drm_match_cea_mode(mode);
struct drm_display_info *display = &connector->display_info;
printk("vic ======== %d-------display->hdmi.scdc.supported = %d",vic,display->hdmi.scdc.supported);
printk("display->hdmi.scdc.scrambling.supported = %d",display->hdmi.scdc.scrambling.supported);
if (vic >= 1)
return MODE_OK;