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drm/i915/gvt: Init vreg GUC_STATUS to GS_MIA_IN_RESET

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Although GVT doesn't support guest GuC, MIA core is still expected
to be GS_MIA_IN_RESET after uc HW reset.

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200819010900.54598-1-colin.xu@intel.com
This commit is contained in:
Colin Xu 2020-08-19 09:09:00 +08:00 • committed by Zhenyu Wang
parent d0a011094a
commit df398e33b8
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/gvt/mmio.c
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@ -251,6 +251,9 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
/* set the bit 0:2(Core C-State ) to C0 */ /* set the bit 0:2(Core C-State ) to C0 */
vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
/* uc reset hw expect GS_MIA_IN_RESET */
vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
if (IS_BROXTON(vgpu->gvt->gt->i915)) { if (IS_BROXTON(vgpu->gvt->gt->i915)) {
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
~(BIT(0) | BIT(1)); ~(BIT(0) | BIT(1));