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ARM: OMAP2+: Drop gpio platform data for omap4
We can now drop legacy platform data one interconnect target module at a time in favor of the device tree based data that has been added earlier. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
f9d34da303
commit
e1c59a3bf6
1 changed files with 0 additions and 207 deletions
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@ -1052,159 +1052,6 @@ static struct omap_hwmod omap44xx_fdif_hwmod = {
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},
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},
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};
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};
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/*
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* 'gpio' class
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* general purpose io module
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0114,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
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.name = "gpio",
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.sysc = &omap44xx_gpio_sysc,
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};
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/* gpio1 */
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static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio1_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio1_hwmod = {
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.name = "gpio1",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "l4_wkup_clk_mux_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio1_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
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};
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/* gpio2 */
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static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio2_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio2_hwmod = {
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.name = "gpio2",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio2_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
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};
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/* gpio3 */
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static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio3_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio3_hwmod = {
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.name = "gpio3",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
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};
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/* gpio4 */
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio4_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio4_hwmod = {
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.name = "gpio4",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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};
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/* gpio5 */
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static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio5_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio5_hwmod = {
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.name = "gpio5",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio5_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
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};
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/* gpio6 */
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static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio6_dbclk" },
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};
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static struct omap_hwmod omap44xx_gpio6_hwmod = {
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.name = "gpio6",
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.class = &omap44xx_gpio_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "l4_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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.opt_clks = gpio6_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
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};
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/*
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/*
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* 'gpmc' class
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* 'gpmc' class
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* general purpose memory controller
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* general purpose memory controller
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@ -3343,54 +3190,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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/* l4_wkup -> gpio1 */
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static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
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.master = &omap44xx_l4_wkup_hwmod,
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.slave = &omap44xx_gpio1_hwmod,
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.clk = "l4_wkup_clk_mux_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio2 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio2_hwmod,
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.clk = "l4_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio3 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio3_hwmod,
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.clk = "l4_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio4 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio4_hwmod,
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.clk = "l4_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio5 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio5_hwmod,
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.clk = "l4_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per -> gpio6 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_gpio6_hwmod,
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.clk = "l4_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_2 -> gpmc */
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/* l3_main_2 -> gpmc */
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static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
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static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
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.master = &omap44xx_l3_main_2_hwmod,
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.master = &omap44xx_l3_main_2_hwmod,
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@ -3937,12 +3736,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_per__dss_venc,
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&omap44xx_l4_per__dss_venc,
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&omap44xx_l4_per__elm,
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&omap44xx_l4_per__elm,
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&omap44xx_l4_cfg__fdif,
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&omap44xx_l4_cfg__fdif,
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&omap44xx_l4_wkup__gpio1,
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&omap44xx_l4_per__gpio2,
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&omap44xx_l4_per__gpio3,
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&omap44xx_l4_per__gpio4,
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&omap44xx_l4_per__gpio5,
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&omap44xx_l4_per__gpio6,
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&omap44xx_l3_main_2__gpmc,
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&omap44xx_l3_main_2__gpmc,
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&omap44xx_l3_main_2__gpu,
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&omap44xx_l3_main_2__gpu,
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&omap44xx_l4_per__hdq1w,
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&omap44xx_l4_per__hdq1w,
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