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platform/chrome: cros_ec: Update mux state bits

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Sync the EC_CMD_USB_PD_MUX_INFO mux state bit fields with the Chrome EC
code base. The newly added bit fields will be used for cros-ec-typec mux
control.

Signed-off-by: Prashant Malani <pmalani@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
This commit is contained in:
Prashant Malani 2020-05-28 04:36:03 -07:00 • committed by Enric Balletbo i Serra
parent f28adb41da
commit e32b16c313
1 changed files with 9 additions and 5 deletions
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14
include/linux/platform_data/cros_ec_commands.h
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@ -5207,11 +5207,15 @@ struct ec_params_usb_pd_mux_info {
} __ec_align1;
/* Flags representing mux state */
#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
#define USB_PD_MUX_NONE 0 /* Open switch */
#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
struct ec_response_usb_pd_mux_info {
uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */