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MIPS: KVM: Report more accurate CP0_Config fields to guest

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Initialise the guest's CP0_Config register with a few more bits of
information from the host. The BE bit should be set on big endian
machines, the VI bit should be set on machines with a virtually tagged
instruction cache, and the reported architecture revision should match
that of the host (since we won't support emulating pre-r6 instruction
encodings on r6 or vice versa).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
James Hogan 2016-06-15 19:30:00 +01:00 • committed by Paolo Bonzini
parent 4b34bca0e4
commit e342925f17
1 changed files with 15 additions and 5 deletions
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20
arch/mips/kvm/trap_emul.c
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@ -426,7 +426,7 @@ static int kvm_trap_emul_vcpu_init(struct kvm_vcpu *vcpu)
static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
{ {
struct mips_coproc *cop0 = vcpu->arch.cop0; struct mips_coproc *cop0 = vcpu->arch.cop0;
u32 config1; u32 config, config1;
int vcpu_id = vcpu->vcpu_id; int vcpu_id = vcpu->vcpu_id;
/* /*
@ -434,10 +434,20 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
* guest will come up as expected, for now we simulate a MIPS 24kc * guest will come up as expected, for now we simulate a MIPS 24kc
*/ */
kvm_write_c0_guest_prid(cop0, 0x00019300); kvm_write_c0_guest_prid(cop0, 0x00019300);
/* Have config1, Cacheable, noncoherent, write-back, write allocate */ /*
kvm_write_c0_guest_config(cop0, MIPS_CONF_M | (0x3 << CP0C0_K0) | * Have config1, Cacheable, noncoherent, write-back, write allocate.
(0x1 << CP0C0_AR) | * Endianness, arch revision & virtually tagged icache should match
(MMU_TYPE_R4000 << CP0C0_MT)); * host.
*/
config = read_c0_config() & MIPS_CONF_AR;
config |= MIPS_CONF_M | (0x3 << CP0C0_K0) |
(MMU_TYPE_R4000 << CP0C0_MT);
#ifdef CONFIG_CPU_BIG_ENDIAN
config |= CONF_BE;
#endif
if (cpu_has_vtag_icache)
config |= MIPS_CONF_VI;
kvm_write_c0_guest_config(cop0, config);
/* Read the cache characteristics from the host Config1 Register */ /* Read the cache characteristics from the host Config1 Register */
config1 = (read_c0_config1() & ~0x7f); config1 = (read_c0_config1() & ~0x7f);