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spi: xilinx: Add DT support for selecting transfer word width

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This core supports either 8, 16 or 32 bits as word width. This value is only
settable on instantiation, and thus we need to support any of them by means
of the device tree.

Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Link: https://lore.kernel.org/r/20191024110757.25820-3-alvaro.gamez@hazent.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Alvaro Gamez Machado 2019-10-24 13:07:56 +02:00 • committed by Mark Brown
parent e3354b17b4
commit e58f7d15e6
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GPG key ID: 24D68B725D5487D0
1 changed files with 6 additions and 1 deletions
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7
drivers/spi/spi-xilinx.c
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@ -391,7 +391,7 @@ static int xilinx_spi_probe(struct platform_device *pdev)
struct xilinx_spi *xspi;
struct xspi_platform_data *pdata;
struct resource *res;
int ret, num_cs = 0, bits_per_word = 8;
int ret, num_cs = 0, bits_per_word;
struct spi_master *master;
u32 tmp;
u8 i;
@ -403,6 +403,11 @@ static int xilinx_spi_probe(struct platform_device *pdev)
} else {
of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
&num_cs);
ret = of_property_read_u32(pdev->dev.of_node,
"xlnx,num-transfer-bits",
&bits_per_word);
if (ret)
bits_per_word = 8;
}
if (!num_cs) {