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PCI/ATS: Cache PRI PRG Response PASID Required bit
The PRG Response PASID Required bit in the PRI Capability is read-only. Read it once when we enumerate the device and cache the value so we don't need to read it again. Based-on-patch-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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2 changed files with 11 additions and 13 deletions
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@ -456,6 +456,7 @@ struct pci_dev {
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#ifdef CONFIG_PCI_PRI
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u16 pri_cap; /* PRI Capability offset */
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u32 pri_reqs_alloc; /* Number of PRI requests allocated */
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unsigned int pasid_required:1; /* PRG Response PASID Required */
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#endif
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#ifdef CONFIG_PCI_PASID
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u16 pasid_cap; /* PASID Capability offset */
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