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MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices

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For a long time the mt7621 uses a fixed cpu clock which causes a problem
if the cpu frequency is not 880MHz.

This patch fixes the cpu clock calculation and adds the cpu/bus clkdev
which will be used in dts.

Ported from OpenWrt:
c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: John Crispin <john@phrozen.org>
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Chuanhong Guo 2019-03-21 22:42:51 +08:00 • committed by Paul Burton
parent e6331a321a
commit e6046b5e69
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GPG key ID: 3EA79FACB57500DD
3 changed files with 93 additions and 33 deletions
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20
arch/mips/include/asm/mach-ralink/mt7621.h
View file

@ -19,6 +19,10 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
#define SYSC_REG_CLKCFG0 0x2c
#define SYSC_REG_CUR_CLK_STS 0x44
#define MEMC_REG_CPU_PLL 0x648
#define CHIP_REV_PKG_MASK 0x1
#define CHIP_REV_PKG_SHIFT 16
@ -26,6 +30,22 @@
#define CHIP_REV_VER_SHIFT 8
#define CHIP_REV_ECO_MASK 0xf
#define XTAL_MODE_SEL_MASK 0x7
#define XTAL_MODE_SEL_SHIFT 6
#define CPU_CLK_SEL_MASK 0x3
#define CPU_CLK_SEL_SHIFT 30
#define CUR_CPU_FDIV_MASK 0x1f
#define CUR_CPU_FDIV_SHIFT 8
#define CUR_CPU_FFRAC_MASK 0x1f
#define CUR_CPU_FFRAC_SHIFT 0
#define CPU_PLL_PREDIV_MASK 0x3
#define CPU_PLL_PREDIV_SHIFT 12
#define CPU_PLL_FBDIV_MASK 0x7f
#define CPU_PLL_FBDIV_SHIFT 4
#define MT7621_DRAM_BASE 0x0
#define MT7621_DDR2_SIZE_MIN 32
#define MT7621_DDR2_SIZE_MAX 256