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ARM: 7922/1: l2x0: add Marvell Tauros3 support

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This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Sebastian Hesselbarth 2013-12-13 16:42:19 +01:00 • committed by Russell King
parent 017f161a55
commit e68f31f452
4 changed files with 94 additions and 19 deletions
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1
arch/arm/include/asm/hardware/cache-l2x0.h
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@ -131,6 +131,7 @@ struct l2x0_regs {
unsigned long prefetch_ctrl;
unsigned long pwr_ctrl;
unsigned long ctrl;
unsigned long aux2_ctrl;
};
extern struct l2x0_regs l2x0_saved_regs;