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Merge branch 'pci/misc'

Browse source 
- Add NumaChip SPDX header (Krzysztof Wilczynski)

  - Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)

  - Remove unused includes (Krzysztof Wilczynski)

  - Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB
    2.0 or 1.1 connect events (Kai-Heng Feng)

  - Removed unused sysfs attribute groups (Ben Dooks)

  - Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)

  - Add PCIe Link Control 2 register field definitions to replace magic
    numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)

  - Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon
    CIK/SI PCIe Gen3 link training (Bjorn Helgaas)

  - Use pcie_capability_read_word() instead of pci_read_config_word() in
    AMDGPU and Radeon CIK/SI (Frederick Lawler)

* pci/misc:
  drm/radeon: Prefer pcie_capability_read_word()
  drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
  drm/radeon: Correct Transmit Margin masks
  drm/amdgpu: Prefer pcie_capability_read_word()
  drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
  drm/amdgpu: Correct Transmit Margin masks
  PCI: Add #defines for Enter Compliance, Transmit Margin
  PCI: Allow building PCIe things without PCIEPORTBUS
  PCI: Remove PCIe Kconfig dependencies on PCI
  PCI/ASPM: Remove dependency on PCIEPORTBUS
  PCI/PTM: Remove dependency on PCIEPORTBUS
  PCI/PTM: Remove spurious "d" from granularity message
  PCI: sysfs: Remove unused attribute groups
  x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect
  PCI: Remove unused includes and superfluous struct declaration
  x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y
  x86/PCI: Correct SPDX comment style
  x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate
This commit is contained in:
Bjorn Helgaas 2019-11-28 08:54:32 -06:00
commit e87eb585d3
23 changed files with 267 additions and 172 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/x86/pci/Makefile
View file

@ -24,6 +24,4 @@ obj-y += bus_numa.o
obj-$(CONFIG_AMD_NB) += amd_bus.o obj-$(CONFIG_AMD_NB) += amd_bus.o
obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o
ifeq ($(CONFIG_PCI_DEBUG),y) ccflags-$(CONFIG_PCI_DEBUG) += -DDEBUG
EXTRA_CFLAGS += -DDEBUG
endif

11
arch/x86/pci/fixup.c
View file

@ -588,6 +588,17 @@ static void pci_fixup_amd_ehci_pme(struct pci_dev *dev)
} }
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
/*
* Device [1022:7914]
* When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
*/
static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
{
dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
/* /*
* Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
* *

5
arch/x86/pci/numachip.c
View file

@ -1,8 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/* /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Numascale NumaConnect-specific PCI code * Numascale NumaConnect-specific PCI code
* *
* Copyright (C) 2012 Numascale AS. All rights reserved. * Copyright (C) 2012 Numascale AS. All rights reserved.

93
drivers/gpu/drm/amd/amdgpu/cik.c
View file

@ -1384,7 +1384,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
static void cik_pcie_gen3_enable(struct amdgpu_device *adev) static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
{ {
struct pci_dev *root = adev->pdev->bus->self; struct pci_dev *root = adev->pdev->bus->self;
int bridge_pos, gpu_pos;
u32 speed_cntl, current_data_rate; u32 speed_cntl, current_data_rate;
int i; int i;
u16 tmp16; u16 tmp16;
@ -1419,12 +1418,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
} }
bridge_pos = pci_pcie_cap(root); if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
if (!bridge_pos)
return;
gpu_pos = pci_pcie_cap(adev->pdev);
if (!gpu_pos)
return; return;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@ -1434,14 +1428,17 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
u16 bridge_cfg2, gpu_cfg2; u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp; u32 max_lw, current_lw, tmp;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@ -1465,15 +1462,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
/* check status */ /* check status */
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); pcie_capability_read_word(adev->pdev,
PCI_EXP_DEVSTA,
&tmp16);
if (tmp16 & PCI_EXP_DEVSTA_TRPND) if (tmp16 & PCI_EXP_DEVSTA_TRPND)
break; break;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&gpu_cfg);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); &bridge_cfg2);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL2,
&gpu_cfg2);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@ -1486,26 +1491,45 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
msleep(100); msleep(100);
/* linkctl */ /* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL,
tmp16);
/* linkctl2 */ /* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
tmp16 &= ~((1 << 4) | (7 << 9)); &tmp16);
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (bridge_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(root,
PCI_EXP_LNKCTL2,
tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(adev->pdev,
tmp16 &= ~((1 << 4) | (7 << 9)); PCI_EXP_LNKCTL2,
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); &tmp16);
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (gpu_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL2,
tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@ -1520,15 +1544,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
tmp16 |= 3; /* gen3 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
tmp16 |= 2; /* gen2 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else else
tmp16 |= 1; /* gen1 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;

93
drivers/gpu/drm/amd/amdgpu/si.c
View file

@ -1633,7 +1633,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
static void si_pcie_gen3_enable(struct amdgpu_device *adev) static void si_pcie_gen3_enable(struct amdgpu_device *adev)
{ {
struct pci_dev *root = adev->pdev->bus->self; struct pci_dev *root = adev->pdev->bus->self;
int bridge_pos, gpu_pos;
u32 speed_cntl, current_data_rate; u32 speed_cntl, current_data_rate;
int i; int i;
u16 tmp16; u16 tmp16;
@ -1668,12 +1667,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
} }
bridge_pos = pci_pcie_cap(root); if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
if (!bridge_pos)
return;
gpu_pos = pci_pcie_cap(adev->pdev);
if (!gpu_pos)
return; return;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@ -1682,14 +1676,17 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
u16 bridge_cfg2, gpu_cfg2; u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp; u32 max_lw, current_lw, tmp;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
tmp16);
tmp = RREG32_PCIE(PCIE_LC_STATUS1); tmp = RREG32_PCIE(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -1706,15 +1703,23 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
} }
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); pcie_capability_read_word(adev->pdev,
PCI_EXP_DEVSTA,
&tmp16);
if (tmp16 & PCI_EXP_DEVSTA_TRPND) if (tmp16 & PCI_EXP_DEVSTA_TRPND)
break; break;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&gpu_cfg);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); &bridge_cfg2);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL2,
&gpu_cfg2);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp |= LC_SET_QUIESCE; tmp |= LC_SET_QUIESCE;
@ -1726,25 +1731,44 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
mdelay(100); mdelay(100);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL,
tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
tmp16 &= ~((1 << 4) | (7 << 9)); &tmp16);
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (bridge_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(root,
PCI_EXP_LNKCTL2,
tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(adev->pdev,
tmp16 &= ~((1 << 4) | (7 << 9)); PCI_EXP_LNKCTL2,
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); &tmp16);
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (gpu_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL2,
tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp &= ~LC_SET_QUIESCE; tmp &= ~LC_SET_QUIESCE;
@ -1757,15 +1781,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
tmp16 |= 3; tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
tmp16 |= 2; tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else else
tmp16 |= 1; tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

92
drivers/gpu/drm/radeon/cik.c
View file

@ -9504,7 +9504,6 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
{ {
struct pci_dev *root = rdev->pdev->bus->self; struct pci_dev *root = rdev->pdev->bus->self;
enum pci_bus_speed speed_cap; enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
u32 speed_cntl, current_data_rate; u32 speed_cntl, current_data_rate;
int i; int i;
u16 tmp16; u16 tmp16;
@ -9546,12 +9545,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
} }
bridge_pos = pci_pcie_cap(root); if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
if (!bridge_pos)
return;
gpu_pos = pci_pcie_cap(rdev->pdev);
if (!gpu_pos)
return; return;
if (speed_cap == PCIE_SPEED_8_0GT) { if (speed_cap == PCIE_SPEED_8_0GT) {
@ -9561,14 +9555,17 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
u16 bridge_cfg2, gpu_cfg2; u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp; u32 max_lw, current_lw, tmp;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -9586,15 +9583,23 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
/* check status */ /* check status */
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); pcie_capability_read_word(rdev->pdev,
PCI_EXP_DEVSTA,
&tmp16);
if (tmp16 & PCI_EXP_DEVSTA_TRPND) if (tmp16 & PCI_EXP_DEVSTA_TRPND)
break; break;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&gpu_cfg);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); &bridge_cfg2);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL2,
&gpu_cfg2);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp |= LC_SET_QUIESCE; tmp |= LC_SET_QUIESCE;
@ -9607,26 +9612,45 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
msleep(100); msleep(100);
/* linkctl */ /* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL,
tmp16);
/* linkctl2 */ /* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
tmp16 &= ~((1 << 4) | (7 << 9)); &tmp16);
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (bridge_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(root,
PCI_EXP_LNKCTL2,
tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(rdev->pdev,
tmp16 &= ~((1 << 4) | (7 << 9)); PCI_EXP_LNKCTL2,
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); &tmp16);
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (gpu_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL2,
tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp &= ~LC_SET_QUIESCE; tmp &= ~LC_SET_QUIESCE;
@ -9640,15 +9664,15 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT) if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT) else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else else
tmp16 |= 1; /* gen1 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

93
drivers/gpu/drm/radeon/si.c
View file

@ -7087,7 +7087,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
{ {
struct pci_dev *root = rdev->pdev->bus->self; struct pci_dev *root = rdev->pdev->bus->self;
enum pci_bus_speed speed_cap; enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
u32 speed_cntl, current_data_rate; u32 speed_cntl, current_data_rate;
int i; int i;
u16 tmp16; u16 tmp16;
@ -7129,12 +7128,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
} }
bridge_pos = pci_pcie_cap(root); if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
if (!bridge_pos)
return;
gpu_pos = pci_pcie_cap(rdev->pdev);
if (!gpu_pos)
return; return;
if (speed_cap == PCIE_SPEED_8_0GT) { if (speed_cap == PCIE_SPEED_8_0GT) {
@ -7144,14 +7138,17 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
u16 bridge_cfg2, gpu_cfg2; u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp; u32 max_lw, current_lw, tmp;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
tmp16);
tmp = RREG32_PCIE(PCIE_LC_STATUS1); tmp = RREG32_PCIE(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -7169,15 +7166,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
/* check status */ /* check status */
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); pcie_capability_read_word(rdev->pdev,
PCI_EXP_DEVSTA,
&tmp16);
if (tmp16 & PCI_EXP_DEVSTA_TRPND) if (tmp16 & PCI_EXP_DEVSTA_TRPND)
break; break;
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); &bridge_cfg);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&gpu_cfg);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); &bridge_cfg2);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL2,
&gpu_cfg2);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp |= LC_SET_QUIESCE; tmp |= LC_SET_QUIESCE;
@ -7190,26 +7195,46 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
msleep(100); msleep(100);
/* linkctl */ /* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(root,
PCI_EXP_LNKCTL,
tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL,
tmp16);
/* linkctl2 */ /* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
tmp16 &= ~((1 << 4) | (7 << 9)); &tmp16);
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (bridge_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(root,
PCI_EXP_LNKCTL2,
tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(rdev->pdev,
tmp16 &= ~((1 << 4) | (7 << 9)); PCI_EXP_LNKCTL2,
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); &tmp16);
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN);
tmp16 |= (gpu_cfg2 &
(PCI_EXP_LNKCTL2_ENTER_COMP |
PCI_EXP_LNKCTL2_TX_MARGIN));
pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL2,
tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
tmp &= ~LC_SET_QUIESCE; tmp &= ~LC_SET_QUIESCE;
@ -7223,15 +7248,15 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT) if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT) else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else else
tmp16 |= 1; /* gen1 */ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

2
drivers/iommu/of_iommu.c
View file

@ -8,6 +8,8 @@
#include <linux/export.h> #include <linux/export.h>
#include <linux/iommu.h> #include <linux/iommu.h>
#include <linux/limits.h> #include <linux/limits.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_iommu.h> #include <linux/of_iommu.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>

1
drivers/irqchip/irq-gic-v2m.c
View file

@ -17,6 +17,7 @@
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h> #include <linux/msi.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>

1
drivers/irqchip/irq-gic-v3-its-pci-msi.c
View file

@ -5,6 +5,7 @@
*/ */
#include <linux/acpi_iort.h> #include <linux/acpi_iort.h>
#include <linux/pci.h>
#include <linux/msi.h> #include <linux/msi.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>

3
drivers/pci/Makefile
View file

@ -7,6 +7,8 @@ obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \
pci-sysfs.o rom.o setup-res.o irq.o vpd.o \ pci-sysfs.o rom.o setup-res.o irq.o vpd.o \
setup-bus.o vc.o mmap.o setup-irq.o setup-bus.o vc.o mmap.o setup-irq.o
obj-$(CONFIG_PCI) += pcie/
ifdef CONFIG_PCI ifdef CONFIG_PCI
obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_SYSFS) += slot.o obj-$(CONFIG_SYSFS) += slot.o
@ -15,7 +17,6 @@ endif
obj-$(CONFIG_OF) += of.o obj-$(CONFIG_OF) += of.o
obj-$(CONFIG_PCI_QUIRKS) += quirks.o obj-$(CONFIG_PCI_QUIRKS) += quirks.o
obj-$(CONFIG_PCIEPORTBUS) += pcie/
obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ obj-$(CONFIG_HOTPLUG_PCI) += hotplug/
obj-$(CONFIG_PCI_MSI) += msi.o obj-$(CONFIG_PCI_MSI) += msi.o
obj-$(CONFIG_PCI_ATS) += ats.o obj-$(CONFIG_PCI_ATS) += ats.o

1
drivers/pci/controller/dwc/pcie-designware-host.c
View file

@ -10,6 +10,7 @@
#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
#include <linux/msi.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/pci_regs.h> #include <linux/pci_regs.h>

1
drivers/pci/controller/pci-aardvark.c
View file

@ -16,6 +16,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/msi.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>

1
drivers/pci/controller/pci-thunder-pem.c
View file

@ -6,6 +6,7 @@
#include <linux/bitfield.h> #include <linux/bitfield.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/pci.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/pci-acpi.h> #include <linux/pci-acpi.h>

2
drivers/pci/controller/pcie-cadence.h
View file

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0 /* SPDX-License-Identifier: GPL-2.0 */
// Copyright (c) 2017 Cadence // Copyright (c) 2017 Cadence
// Cadence PCIe controller driver. // Cadence PCIe controller driver.
// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>

2
drivers/pci/controller/pcie-rockchip.h
View file

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* Rockchip AXI PCIe controller driver * Rockchip AXI PCIe controller driver
* *

18
drivers/pci/pci-sysfs.c
View file

@ -1536,24 +1536,6 @@ const struct attribute_group *pci_dev_groups[] = {
NULL, NULL,
}; };
static const struct attribute_group pci_bridge_group = {
.attrs = pci_bridge_attrs,
};
const struct attribute_group *pci_bridge_groups[] = {
&pci_bridge_group,
NULL,
};
static const struct attribute_group pcie_dev_group = {
.attrs = pcie_dev_attrs,
};
const struct attribute_group *pcie_dev_groups[] = {
&pcie_dev_group,
NULL,
};
static const struct attribute_group pci_dev_hp_attr_group = { static const struct attribute_group pci_dev_hp_attr_group = {
.attrs = pci_dev_hp_attrs, .attrs = pci_dev_hp_attrs,
.is_visible = pci_dev_hp_attrs_are_visible, .is_visible = pci_dev_hp_attrs_are_visible,

1
drivers/pci/pci.c
View file

@ -13,6 +13,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/dmi.h> #include <linux/dmi.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/msi.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/pci.h> #include <linux/pci.h>

3
drivers/pci/pcie/Kconfig
View file

@ -4,7 +4,6 @@
# #
config PCIEPORTBUS config PCIEPORTBUS
bool "PCI Express Port Bus support" bool "PCI Express Port Bus support"
depends on PCI
help help
This enables PCI Express Port Bus support. Users can then enable This enables PCI Express Port Bus support. Users can then enable
support for Native Hot-Plug, Advanced Error Reporting, Power support for Native Hot-Plug, Advanced Error Reporting, Power
@ -63,7 +62,6 @@ config PCIE_ECRC
# #
config PCIEASPM config PCIEASPM
bool "PCI Express ASPM control" if EXPERT bool "PCI Express ASPM control" if EXPERT
depends on PCI && PCIEPORTBUS
default y default y
help help
This enables OS control over PCI Express ASPM (Active State This enables OS control over PCI Express ASPM (Active State
@ -128,7 +126,6 @@ config PCIE_DPC
config PCIE_PTM config PCIE_PTM
bool "PCI Express Precision Time Measurement support" bool "PCI Express Precision Time Measurement support"
depends on PCIEPORTBUS
help help
This enables PCI Express Precision Time Measurement (PTM) This enables PCI Express Precision Time Measurement (PTM)
support. support.

2
drivers/pci/pcie/ptm.c
View file

@ -21,7 +21,7 @@ static void pci_ptm_info(struct pci_dev *dev)
snprintf(clock_desc, sizeof(clock_desc), ">254ns"); snprintf(clock_desc, sizeof(clock_desc), ">254ns");
break; break;
default: default:
snprintf(clock_desc, sizeof(clock_desc), "%udns", snprintf(clock_desc, sizeof(clock_desc), "%uns",
dev->ptm_granularity); dev->ptm_granularity);
break; break;
} }

1
drivers/pci/probe.c
View file

@ -7,6 +7,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/msi.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/pci_hotplug.h> #include <linux/pci_hotplug.h>

5
include/linux/of_pci.h
View file

@ -2,11 +2,10 @@
#ifndef __OF_PCI_H #ifndef __OF_PCI_H
#define __OF_PCI_H #define __OF_PCI_H
#include <linux/pci.h> #include <linux/types.h>
#include <linux/msi.h> #include <linux/errno.h>
struct pci_dev; struct pci_dev;
struct of_phandle_args;
struct device_node; struct device_node;
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI) #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI)

2
include/uapi/linux/pci_regs.h
View file

@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */