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pwm: opencores: Add PWM driver support
Add driver for OpenCores PWM Controller. And add compatibility code which based on StarFive SoC. Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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3 changed files with 246 additions and 0 deletions
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@ -434,6 +434,18 @@ config PWM_NTXEC
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controller found in certain e-book readers designed by the original
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design manufacturer Netronix.
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config PWM_OCORES
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tristate "OpenCores PWM support"
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depends on HAS_IOMEM && OF
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depends on COMMON_CLK
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depends on ARCH_STARFIVE || COMPILE_TEST
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help
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If you say yes to this option, support will be included for the
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OpenCores PWM. For details see https://opencores.org/projects/ptc.
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To compile this driver as a module, choose M here: the module
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will be called pwm-ocores.
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config PWM_OMAP_DMTIMER
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tristate "OMAP Dual-Mode Timer PWM support"
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depends on OF
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@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
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obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
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obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
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obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
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obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
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obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
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obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
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obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
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233
drivers/pwm/pwm-ocores.c
Normal file
233
drivers/pwm/pwm-ocores.c
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@ -0,0 +1,233 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* OpenCores PWM Driver
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*
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* https://opencores.org/projects/ptc
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*
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* Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
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*
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* Limitations:
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* - The hardware only do inverted polarity.
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* - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns.
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* - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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/* OCPWM_CTRL register bits*/
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#define REG_OCPWM_EN BIT(0)
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#define REG_OCPWM_ECLK BIT(1)
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#define REG_OCPWM_NEC BIT(2)
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#define REG_OCPWM_OE BIT(3)
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#define REG_OCPWM_SIGNLE BIT(4)
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#define REG_OCPWM_INTE BIT(5)
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#define REG_OCPWM_INT BIT(6)
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#define REG_OCPWM_CNTRRST BIT(7)
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#define REG_OCPWM_CAPTE BIT(8)
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struct ocores_pwm_device {
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struct pwm_chip chip;
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struct clk *clk;
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struct reset_control *rst;
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const struct ocores_pwm_data *data;
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void __iomem *regs;
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u32 clk_rate; /* PWM APB clock frequency */
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};
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struct ocores_pwm_data {
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void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel);
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};
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static inline u32 ocores_readl(struct ocores_pwm_device *ddata,
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unsigned int channel,
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unsigned int offset)
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{
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void __iomem *base = ddata->data->get_ch_base ?
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ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs;
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return readl(base + offset);
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}
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static inline void ocores_writel(struct ocores_pwm_device *ddata,
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unsigned int channel,
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unsigned int offset, u32 val)
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{
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void __iomem *base = ddata->data->get_ch_base ?
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ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs;
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writel(val, base + offset);
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}
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static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *chip)
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{
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return container_of(chip, struct ocores_pwm_device, chip);
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}
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static void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base,
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unsigned int channel)
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{
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unsigned int offset = (channel > 3 ? 1 << 15 : 0) + (channel & 3) * 0x10;
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return base + offset;
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}
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static int ocores_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct ocores_pwm_device *ddata = chip_to_ocores(chip);
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u32 period_data, duty_data, ctrl_data;
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period_data = ocores_readl(ddata, pwm->hwpwm, 0x8);
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duty_data = ocores_readl(ddata, pwm->hwpwm, 0x4);
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ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
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state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate);
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state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate);
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state->polarity = PWM_POLARITY_INVERSED;
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state->enabled = (ctrl_data & REG_OCPWM_EN) ? true : false;
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return 0;
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}
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static int ocores_pwm_apply(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct ocores_pwm_device *ddata = chip_to_ocores(chip);
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u32 ctrl_data = 0;
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u64 period_data, duty_data;
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if (state->polarity != PWM_POLARITY_INVERSED)
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return -EINVAL;
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ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
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ocores_writel(ddata, pwm->hwpwm, 0xC, 0);
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period_data = DIV_ROUND_DOWN_ULL(state->period * ddata->clk_rate, NSEC_PER_SEC);
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if (period_data <= U32_MAX)
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ocores_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data);
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else
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return -EINVAL;
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duty_data = DIV_ROUND_DOWN_ULL(state->duty_cycle * ddata->clk_rate, NSEC_PER_SEC);
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if (duty_data <= U32_MAX)
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ocores_writel(ddata, pwm->hwpwm, 0x4, (u32)duty_data);
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else
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return -EINVAL;
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ocores_writel(ddata, pwm->hwpwm, 0xC, 0);
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if (state->enabled) {
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ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
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ocores_writel(ddata, pwm->hwpwm, 0xC, ctrl_data | REG_OCPWM_EN | REG_OCPWM_OE);
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}
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return 0;
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}
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static const struct pwm_ops ocores_pwm_ops = {
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.get_state = ocores_pwm_get_state,
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.apply = ocores_pwm_apply,
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};
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static const struct ocores_pwm_data jh7100_pwm_data = {
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.get_ch_base = starfive_jh71x0_get_ch_base,
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};
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static const struct ocores_pwm_data jh7110_pwm_data = {
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.get_ch_base = starfive_jh71x0_get_ch_base,
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};
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static const struct of_device_id ocores_pwm_of_match[] = {
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{ .compatible = "opencores,pwm-v1" },
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{ .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data},
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{ .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, ocores_pwm_of_match);
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static void ocores_reset_control_assert(void *data)
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{
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reset_control_assert(data);
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}
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static int ocores_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct device *dev = &pdev->dev;
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struct ocores_pwm_device *ddata;
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struct pwm_chip *chip;
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int ret;
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id = of_match_device(ocores_pwm_of_match, dev);
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if (!id)
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return -EINVAL;
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ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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ddata->data = id->data;
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chip = &ddata->chip;
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chip->dev = dev;
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chip->ops = &ocores_pwm_ops;
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chip->npwm = 8;
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chip->of_pwm_n_cells = 3;
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ddata->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ddata->regs))
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return dev_err_probe(dev, PTR_ERR(ddata->regs),
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"Unable to map IO resources\n");
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ddata->clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(ddata->clk))
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return dev_err_probe(dev, PTR_ERR(ddata->clk),
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"Unable to get pwm's clock\n");
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ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(ddata->rst))
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return dev_err_probe(dev, PTR_ERR(ddata->rst),
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"Unable to get pwm's reset\n");
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reset_control_deassert(ddata->rst);
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ret = devm_add_action_or_reset(dev, ocores_reset_control_assert, ddata->rst);
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if (ret)
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return ret;
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ddata->clk_rate = clk_get_rate(ddata->clk);
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if (ddata->clk_rate <= 0)
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return dev_err_probe(dev, ddata->clk_rate,
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"Unable to get clock's rate\n");
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ret = devm_pwmchip_add(dev, chip);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Could not register PWM chip\n");
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platform_set_drvdata(pdev, ddata);
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return ret;
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}
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static struct platform_driver ocores_pwm_driver = {
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.probe = ocores_pwm_probe,
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.driver = {
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.name = "ocores-pwm",
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.of_match_table = ocores_pwm_of_match,
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},
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};
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module_platform_driver(ocores_pwm_driver);
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MODULE_AUTHOR("Jieqin Chen");
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MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
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MODULE_DESCRIPTION("OpenCores PWM PTC driver");
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MODULE_LICENSE("GPL");
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