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Merge branch 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next

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just a few minor fixes for radeon.

* 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux:
  radeon: use max_bus_speed to activate gen2 speeds
  drm/radeon: narrow scope of Apple re-POST hack
  drm/radeon: don't check crtcs in card_posted() on cards without DCE
  drm/radeon: fix card_posted check for newer asics
  drm/radeon: fix typo in cu_per_sh on verde
  drm/radeon: UVD block on SUMO2 is the same as on SUMO
This commit is contained in:
Dave Airlie 2013-05-30 09:14:03 +10:00
commit e9a0a3adc2
5 changed files with 25 additions and 36 deletions
Download patch file Download diff file Expand all files Collapse all files

10
drivers/gpu/drm/radeon/evergreen.c
View file

@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev)
void evergreen_pcie_gen2_enable(struct radeon_device *rdev) void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
{ {
u32 link_width_cntl, speed_cntl, mask; u32 link_width_cntl, speed_cntl;
int ret;
if (radeon_pcie_gen2 == 0) if (radeon_pcie_gen2 == 0)
return; return;
@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev)) if (ASIC_IS_X2(rdev))
return; return;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
if (ret != 0) (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
return;
if (!(mask & DRM_PCIE_SPEED_50))
return; return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

9
drivers/gpu/drm/radeon/r600.c
View file

@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
{ {
u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
u16 link_cntl2; u16 link_cntl2;
u32 mask;
int ret;
if (radeon_pcie_gen2 == 0) if (radeon_pcie_gen2 == 0)
return; return;
@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
if (rdev->family <= CHIP_R600) if (rdev->family <= CHIP_R600)
return; return;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
if (ret != 0) (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
return;
if (!(mask & DRM_PCIE_SPEED_50))
return; return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

27
drivers/gpu/drm/radeon/radeon_device.c
View file

@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev)
{ {
uint32_t reg; uint32_t reg;
/* required for EFI mode on macbook2,1 which uses an r5xx asic */
if (efi_enabled(EFI_BOOT) && if (efi_enabled(EFI_BOOT) &&
rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
(rdev->family < CHIP_R600))
return false; return false;
if (ASIC_IS_NODCE(rdev))
goto check_memsize;
/* first check CRTCs */ /* first check CRTCs */
if (ASIC_IS_DCE41(rdev)) { if (ASIC_IS_DCE4(rdev)) {
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
if (reg & EVERGREEN_CRTC_MASTER_EN) if (rdev->num_crtc >= 4) {
return true; reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
} else if (ASIC_IS_DCE4(rdev)) { RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | }
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | if (rdev->num_crtc >= 6) {
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | }
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
if (reg & EVERGREEN_CRTC_MASTER_EN) if (reg & EVERGREEN_CRTC_MASTER_EN)
return true; return true;
} else if (ASIC_IS_AVIVO(rdev)) { } else if (ASIC_IS_AVIVO(rdev)) {
@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev)
} }
} }
check_memsize:
/* then check MEM_SIZE, in case the crtcs are off */ /* then check MEM_SIZE, in case the crtcs are off */
if (rdev->family >= CHIP_R600) if (rdev->family >= CHIP_R600)
reg = RREG32(R600_CONFIG_MEMSIZE); reg = RREG32(R600_CONFIG_MEMSIZE);

13
drivers/gpu/drm/radeon/rv770.c
View file

@ -862,10 +862,8 @@ int rv770_uvd_resume(struct radeon_device *rdev)
chip_id = 0x0100000b; chip_id = 0x0100000b;
break; break;
case CHIP_SUMO: case CHIP_SUMO:
chip_id = 0x0100000c;
break;
case CHIP_SUMO2: case CHIP_SUMO2:
chip_id = 0x0100000d; chip_id = 0x0100000c;
break; break;
case CHIP_PALM: case CHIP_PALM:
chip_id = 0x0100000e; chip_id = 0x0100000e;
@ -2113,8 +2111,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
{ {
u32 link_width_cntl, lanes, speed_cntl, tmp; u32 link_width_cntl, lanes, speed_cntl, tmp;
u16 link_cntl2; u16 link_cntl2;
u32 mask;
int ret;
if (radeon_pcie_gen2 == 0) if (radeon_pcie_gen2 == 0)
return; return;
@ -2129,11 +2125,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev)) if (ASIC_IS_X2(rdev))
return; return;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
if (ret != 0) (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
return;
if (!(mask & DRM_PCIE_SPEED_50))
return; return;
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

2
drivers/gpu/drm/radeon/si.c
View file

@ -2616,7 +2616,7 @@ static void si_gpu_init(struct radeon_device *rdev)
default: default:
rdev->config.si.max_shader_engines = 1; rdev->config.si.max_shader_engines = 1;
rdev->config.si.max_tile_pipes = 4; rdev->config.si.max_tile_pipes = 4;
rdev->config.si.max_cu_per_sh = 2; rdev->config.si.max_cu_per_sh = 5;
rdev->config.si.max_sh_per_se = 2; rdev->config.si.max_sh_per_se = 2;
rdev->config.si.max_backends_per_se = 4; rdev->config.si.max_backends_per_se = 4;
rdev->config.si.max_texture_channel_caches = 4; rdev->config.si.max_texture_channel_caches = 4;