mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-07-23 23:32:14 +00:00
Merge remote-tracking branch 'agust/next' into next
<< Switch mpc512x to the common clock framework and adapt mpc512x drivers to use the new clock driver. Old PPC_CLOCK code is removed entirely since there are no users any more. >>
This commit is contained in:
Benjamin Herrenschmidt
commit
e9a371100d
22 changed files with 1839 additions and 1093 deletions
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@ -139,7 +139,14 @@
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};
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};
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clocks {
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osc {
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clock-frequency = <25000000>;
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};
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};
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soc@80000000 {
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bus-frequency = <80000000>; /* 80 MHz ips bus */
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clock@f00 {
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compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
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@ -9,6 +9,8 @@
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* option) any later version.
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*/
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#include <dt-bindings/clock/mpc512x-clock.h>
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/dts-v1/;
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/ {
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@ -49,6 +51,10 @@
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compatible = "fsl,mpc5121-mbx";
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reg = <0x20000000 0x4000>;
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interrupts = <66 0x8>;
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clocks = <&clks MPC512x_CLK_MBX_BUS>,
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<&clks MPC512x_CLK_MBX_3D>,
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<&clks MPC512x_CLK_MBX>;
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clock-names = "mbx-bus", "mbx-3d", "mbx";
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};
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sram@30000000 {
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@ -62,6 +68,8 @@
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interrupts = <6 8>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&clks MPC512x_CLK_NFC>;
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clock-names = "ipg";
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};
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localbus@80000020 {
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@ -73,6 +81,17 @@
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ranges = <0x0 0x0 0xfc000000 0x04000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33000000>;
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};
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};
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soc@80000000 {
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compatible = "fsl,mpc5121-immr";
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#address-cells = <1>;
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@ -117,9 +136,12 @@
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};
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/* Clock control */
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clock@f00 {
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clks: clock@f00 {
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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#clock-cells = <1>;
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clocks = <&osc>;
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clock-names = "osc";
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};
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/* Power Management Controller */
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@ -139,12 +161,24 @@
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compatible = "fsl,mpc5121-mscan";
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reg = <0x1300 0x80>;
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interrupts = <12 0x8>;
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clocks = <&clks MPC512x_CLK_BDLC>,
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<&clks MPC512x_CLK_IPS>,
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<&clks MPC512x_CLK_SYS>,
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<&clks MPC512x_CLK_REF>,
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<&clks MPC512x_CLK_MSCAN0_MCLK>;
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clock-names = "ipg", "ips", "sys", "ref", "mclk";
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};
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can@1380 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x1380 0x80>;
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interrupts = <13 0x8>;
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clocks = <&clks MPC512x_CLK_BDLC>,
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<&clks MPC512x_CLK_IPS>,
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<&clks MPC512x_CLK_SYS>,
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<&clks MPC512x_CLK_REF>,
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<&clks MPC512x_CLK_MSCAN1_MCLK>;
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clock-names = "ipg", "ips", "sys", "ref", "mclk";
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};
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sdhc@1500 {
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@ -153,6 +187,9 @@
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interrupts = <8 0x8>;
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dmas = <&dma0 30>;
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dma-names = "rx-tx";
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clocks = <&clks MPC512x_CLK_IPS>,
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<&clks MPC512x_CLK_SDHC>;
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clock-names = "ipg", "per";
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};
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i2c@1700 {
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@ -161,6 +198,8 @@
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1700 0x20>;
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interrupts = <9 0x8>;
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clocks = <&clks MPC512x_CLK_I2C>;
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clock-names = "ipg";
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};
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i2c@1720 {
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@ -169,6 +208,8 @@
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1720 0x20>;
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interrupts = <10 0x8>;
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clocks = <&clks MPC512x_CLK_I2C>;
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clock-names = "ipg";
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};
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i2c@1740 {
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@ -177,6 +218,8 @@
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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clocks = <&clks MPC512x_CLK_I2C>;
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clock-names = "ipg";
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};
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i2ccontrol@1760 {
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@ -188,30 +231,48 @@
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compatible = "fsl,mpc5121-axe";
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reg = <0x2000 0x100>;
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interrupts = <42 0x8>;
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clocks = <&clks MPC512x_CLK_AXE>;
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clock-names = "ipg";
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};
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display@2100 {
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compatible = "fsl,mpc5121-diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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clocks = <&clks MPC512x_CLK_DIU>;
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clock-names = "ipg";
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};
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can@2300 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x2300 0x80>;
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interrupts = <90 0x8>;
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clocks = <&clks MPC512x_CLK_BDLC>,
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<&clks MPC512x_CLK_IPS>,
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<&clks MPC512x_CLK_SYS>,
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<&clks MPC512x_CLK_REF>,
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<&clks MPC512x_CLK_MSCAN2_MCLK>;
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clock-names = "ipg", "ips", "sys", "ref", "mclk";
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};
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can@2380 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x2380 0x80>;
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interrupts = <91 0x8>;
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clocks = <&clks MPC512x_CLK_BDLC>,
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<&clks MPC512x_CLK_IPS>,
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<&clks MPC512x_CLK_SYS>,
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<&clks MPC512x_CLK_REF>,
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<&clks MPC512x_CLK_MSCAN3_MCLK>;
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clock-names = "ipg", "ips", "sys", "ref", "mclk";
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};
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viu@2400 {
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compatible = "fsl,mpc5121-viu";
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reg = <0x2400 0x400>;
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interrupts = <67 0x8>;
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clocks = <&clks MPC512x_CLK_VIU>;
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clock-names = "ipg";
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};
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mdio@2800 {
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@ -219,6 +280,8 @@
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reg = <0x2800 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks MPC512x_CLK_FEC>;
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clock-names = "per";
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};
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eth0: ethernet@2800 {
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@ -227,6 +290,8 @@
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reg = <0x2800 0x800>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <4 0x8>;
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clocks = <&clks MPC512x_CLK_FEC>;
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clock-names = "per";
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};
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/* USB1 using external ULPI PHY */
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@ -238,6 +303,8 @@
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interrupts = <43 0x8>;
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dr_mode = "otg";
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phy_type = "ulpi";
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clocks = <&clks MPC512x_CLK_USB1>;
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clock-names = "ipg";
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};
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/* USB0 using internal UTMI PHY */
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@ -249,6 +316,8 @@
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interrupts = <44 0x8>;
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dr_mode = "otg";
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phy_type = "utmi_wide";
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clocks = <&clks MPC512x_CLK_USB2>;
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clock-names = "ipg";
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};
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/* IO control */
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@ -267,6 +336,8 @@
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compatible = "fsl,mpc5121-pata";
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reg = <0x10200 0x100>;
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interrupts = <5 0x8>;
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clocks = <&clks MPC512x_CLK_PATA>;
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clock-names = "ipg";
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};
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/* 512x PSCs are not 52xx PSC compatible */
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@ -278,6 +349,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC0>,
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<&clks MPC512x_CLK_PSC0_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC1 */
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@ -287,6 +361,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC1>,
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<&clks MPC512x_CLK_PSC1_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC2 */
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@ -296,6 +373,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC2>,
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<&clks MPC512x_CLK_PSC2_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC3 */
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@ -305,6 +385,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC3>,
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<&clks MPC512x_CLK_PSC3_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC4 */
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@ -314,6 +397,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC4>,
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<&clks MPC512x_CLK_PSC4_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC5 */
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@ -323,6 +409,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC5>,
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<&clks MPC512x_CLK_PSC5_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC6 */
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@ -332,6 +421,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC6>,
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<&clks MPC512x_CLK_PSC6_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC7 */
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@ -341,6 +433,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC7>,
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<&clks MPC512x_CLK_PSC7_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC8 */
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@ -350,6 +445,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC8>,
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<&clks MPC512x_CLK_PSC8_MCLK>;
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clock-names = "ipg", "mclk";
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};
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/* PSC9 */
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|
|
@ -359,6 +457,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC9>,
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<&clks MPC512x_CLK_PSC9_MCLK>;
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clock-names = "ipg", "mclk";
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};
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|
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/* PSC10 */
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|
|
@ -368,6 +469,9 @@
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC10>,
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<&clks MPC512x_CLK_PSC10_MCLK>;
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clock-names = "ipg", "mclk";
|
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};
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|
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/* PSC11 */
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|
|
@ -377,12 +481,17 @@
|
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interrupts = <40 0x8>;
|
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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clocks = <&clks MPC512x_CLK_PSC11>,
|
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<&clks MPC512x_CLK_PSC11_MCLK>;
|
||||
clock-names = "ipg", "mclk";
|
||||
};
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||||
|
||||
pscfifo@11f00 {
|
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compatible = "fsl,mpc5121-psc-fifo";
|
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reg = <0x11f00 0x100>;
|
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interrupts = <40 0x8>;
|
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clocks = <&clks MPC512x_CLK_PSC_FIFO>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
dma0: dma@14000 {
|
||||
|
|
@ -400,6 +509,8 @@
|
|||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clks MPC512x_CLK_PCI>;
|
||||
clock-names = "ipg";
|
||||
|
||||
reg = <0x80008500 0x100 /* internal registers */
|
||||
0x80008300 0x8>; /* config space access registers */
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/mpc512x-clock.h>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
|
|
@ -54,6 +56,17 @@
|
|||
reg = <0x30000000 0x08000>; // 32K at 0x30000000
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <33000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@80000000 {
|
||||
compatible = "fsl,mpc5121-immr";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -87,9 +100,12 @@
|
|||
reg = <0xe00 0x100>;
|
||||
};
|
||||
|
||||
clock@f00 { // Clock control
|
||||
clks: clock@f00 { // Clock control
|
||||
compatible = "fsl,mpc5121-clock";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc>;
|
||||
clock-names = "osc";
|
||||
};
|
||||
|
||||
pmc@1000{ // Power Management Controller
|
||||
|
|
@ -114,18 +130,33 @@
|
|||
compatible = "fsl,mpc5121-mscan";
|
||||
interrupts = <12 0x8>;
|
||||
reg = <0x1300 0x80>;
|
||||
clocks = <&clks MPC512x_CLK_BDLC>,
|
||||
<&clks MPC512x_CLK_IPS>,
|
||||
<&clks MPC512x_CLK_SYS>,
|
||||
<&clks MPC512x_CLK_REF>,
|
||||
<&clks MPC512x_CLK_MSCAN0_MCLK>;
|
||||
clock-names = "ipg", "ips", "sys", "ref", "mclk";
|
||||
};
|
||||
|
||||
can@1380 {
|
||||
compatible = "fsl,mpc5121-mscan";
|
||||
interrupts = <13 0x8>;
|
||||
reg = <0x1380 0x80>;
|
||||
clocks = <&clks MPC512x_CLK_BDLC>,
|
||||
<&clks MPC512x_CLK_IPS>,
|
||||
<&clks MPC512x_CLK_SYS>,
|
||||
<&clks MPC512x_CLK_REF>,
|
||||
<&clks MPC512x_CLK_MSCAN1_MCLK>;
|
||||
clock-names = "ipg", "ips", "sys", "ref", "mclk";
|
||||
};
|
||||
|
||||
sdhc@1500 {
|
||||
compatible = "fsl,mpc5121-sdhc";
|
||||
interrupts = <8 0x8>;
|
||||
reg = <0x1500 0x100>;
|
||||
clocks = <&clks MPC512x_CLK_IPS>,
|
||||
<&clks MPC512x_CLK_SDHC>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
i2c@1700 {
|
||||
|
|
@ -134,6 +165,8 @@
|
|||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
reg = <0x1700 0x20>;
|
||||
interrupts = <0x9 0x8>;
|
||||
clocks = <&clks MPC512x_CLK_I2C>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
i2c@1720 {
|
||||
|
|
@ -142,6 +175,8 @@
|
|||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
reg = <0x1720 0x20>;
|
||||
interrupts = <0xa 0x8>;
|
||||
clocks = <&clks MPC512x_CLK_I2C>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
i2c@1740 {
|
||||
|
|
@ -150,6 +185,8 @@
|
|||
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
||||
reg = <0x1740 0x20>;
|
||||
interrupts = <0xb 0x8>;
|
||||
clocks = <&clks MPC512x_CLK_I2C>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
i2ccontrol@1760 {
|
||||
|
|
@ -161,6 +198,8 @@
|
|||
compatible = "fsl,mpc5121-diu";
|
||||
reg = <0x2100 0x100>;
|
||||
interrupts = <64 0x8>;
|
||||
clocks = <&clks MPC512x_CLK_DIU>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
mdio@2800 {
|
||||
|
|
@ -180,6 +219,8 @@
|
|||
interrupts = <4 0x8>;
|
||||
phy-handle = < &phy0 >;
|
||||
phy-connection-type = "rmii";
|
||||
clocks = <&clks MPC512x_CLK_FEC>;
|
||||
clock-names = "per";
|
||||
};
|
||||
|
||||
// IO control
|
||||
|
|
@ -200,6 +241,8 @@
|
|||
interrupts = <43 0x8>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
clocks = <&clks MPC512x_CLK_USB1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -211,6 +254,9 @@
|
|||
interrupts = <40 0x8>;
|
||||
fsl,rx-fifo-size = <16>;
|
||||
fsl,tx-fifo-size = <16>;
|
||||
clocks = <&clks MPC512x_CLK_PSC1>,
|
||||
<&clks MPC512x_CLK_PSC1_MCLK>;
|
||||
clock-names = "ipg", "mclk";
|
||||
};
|
||||
|
||||
// PSC9 uart1 aka ttyPSC1
|
||||
|
|
@ -220,12 +266,17 @@
|
|||
interrupts = <40 0x8>;
|
||||
fsl,rx-fifo-size = <16>;
|
||||
fsl,tx-fifo-size = <16>;
|
||||
clocks = <&clks MPC512x_CLK_PSC9>,
|
||||
<&clks MPC512x_CLK_PSC9_MCLK>;
|
||||
clock-names = "ipg", "mclk";
|
||||
};
|
||||
|
||||
pscfifo@11f00 {
|
||||
compatible = "fsl,mpc5121-psc-fifo";
|
||||
reg = <0x11f00 0x100>;
|
||||
interrupts = <40 0x8>;
|
||||
clocks = <&clks MPC512x_CLK_PSC_FIFO>;
|
||||
clock-names = "ipg";
|
||||
};
|
||||
|
||||
dma@14000 {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue