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drm/amd/display: Move MAX_TMDS_CLOCK define to header

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Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2017-12-04 20:58:16 -05:00 • committed by Alex Deucher
parent 91178796ba
commit eb6c24a3e6
4 changed files with 5 additions and 15 deletions
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3
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View file

@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged(
return true; return true;
} }
/* Maximum TMDS single link pixel clock 165MHz */
#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
static void update_stream_engine_usage( static void update_stream_engine_usage(
struct resource_context *res_ctx, struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,

7
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View file

@ -82,13 +82,6 @@
#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
#define TMDS_MIN_PIXEL_CLOCK 25000
/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
#define TMDS_MAX_PIXEL_CLOCK 165000
/* For current ASICs pixel clock - 600MHz */
#define MAX_ENCODER_CLOCK 600000
enum { enum {
DP_MST_UPDATE_MAX_RETRY = 50 DP_MST_UPDATE_MAX_RETRY = 50
}; };

5
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
View file

@ -419,11 +419,6 @@ struct bios_event_info {
bool backlight_changed; bool backlight_changed;
}; };
enum {
HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
};
/* /*
* DFS-bypass flag * DFS-bypass flag
*/ */

5
drivers/gpu/drm/amd/display/include/signal_types.h
View file

@ -26,6 +26,11 @@
#ifndef __DC_SIGNAL_TYPES_H__ #ifndef __DC_SIGNAL_TYPES_H__
#define __DC_SIGNAL_TYPES_H__ #define __DC_SIGNAL_TYPES_H__
/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
#define TMDS_MIN_PIXEL_CLOCK 25000
/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
#define TMDS_MAX_PIXEL_CLOCK 165000
enum signal_type { enum signal_type {
SIGNAL_TYPE_NONE = 0L, /* no signal */ SIGNAL_TYPE_NONE = 0L, /* no signal */
SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0), SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),