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drm/i915: Remove superfluous posting reads after clear GGTT

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The barrier here is not required - we apply the barrier before the range
is ever reused by the GPU instead.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170215084357.19977-16-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2017-02-15 08:43:50 +00:00
parent c5d092a429
commit ec151f31cd
1 changed files with 0 additions and 3 deletions
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3
drivers/gpu/drm/i915/i915_gem_gtt.c
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@ -2184,7 +2184,6 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
for (i = 0; i < num_entries; i++) for (i = 0; i < num_entries; i++)
gen8_set_pte(&gtt_base[i], scratch_pte); gen8_set_pte(&gtt_base[i], scratch_pte);
readl(gtt_base);
} }
static void gen6_ggtt_clear_range(struct i915_address_space *vm, static void gen6_ggtt_clear_range(struct i915_address_space *vm,
@ -2209,7 +2208,6 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
for (i = 0; i < num_entries; i++) for (i = 0; i < num_entries; i++)
iowrite32(scratch_pte, &gtt_base[i]); iowrite32(scratch_pte, &gtt_base[i]);
readl(gtt_base);
} }
static void i915_ggtt_insert_page(struct i915_address_space *vm, static void i915_ggtt_insert_page(struct i915_address_space *vm,
@ -2233,7 +2231,6 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
} }
static void i915_ggtt_clear_range(struct i915_address_space *vm, static void i915_ggtt_clear_range(struct i915_address_space *vm,