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drm/nvd0/disp: implement support for older DISP_SYNC classes

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-11-16 13:16:51 +10:00
parent 419e8dc0af
commit ed5085a589
1 changed files with 43 additions and 19 deletions
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62
drivers/gpu/drm/nouveau/nvd0_display.c
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@ -390,7 +390,6 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
struct nvd0_disp *disp = nvd0_disp(crtc->dev); struct nvd0_disp *disp = nvd0_disp(crtc->dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nvd0_sync *sync = nvd0_sync(crtc); struct nvd0_sync *sync = nvd0_sync(crtc);
u64 offset;
u32 *push; u32 *push;
int ret; int ret;
@ -408,20 +407,36 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
if (ret) if (ret)
return ret; return ret;
if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
OUT_RING (chan, sync->sem.offset);
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
OUT_RING (chan, sync->sem.offset ^ 0x10);
OUT_RING (chan, 0x74b1e000);
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
if (nv_mclass(chan->object) < NV84_CHANNEL_DMA_CLASS)
OUT_RING (chan, NvSema);
else
OUT_RING (chan, chan->vram);
} else {
u64 offset = nvc0_fence_crtc(chan, nv_crtc->index);
offset += sync->sem.offset;
offset = nvc0_fence_crtc(chan, nv_crtc->index); BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
offset += sync->sem.offset; OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset));
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
OUT_RING (chan, 0x1002);
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset ^ 0x10));
OUT_RING (chan, 0x74b1e000);
OUT_RING (chan, 0x1001);
}
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset));
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
OUT_RING (chan, 0x1002);
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset ^ 0x10));
OUT_RING (chan, 0x74b1e000);
OUT_RING (chan, 0x1001);
FIRE_RING (chan); FIRE_RING (chan);
} else { } else {
nouveau_bo_wr32(disp->sync, sync->sem.offset / 4, nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
@ -451,12 +466,21 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
evo_mthd(push, 0x0110, 2); evo_mthd(push, 0x0110, 2);
evo_data(push, 0x00000000); evo_data(push, 0x00000000);
evo_data(push, 0x00000000); evo_data(push, 0x00000000);
evo_mthd(push, 0x0400, 5); if (nvd0_vers(sync) < NVD0_DISP_SYNC_CLASS) {
evo_data(push, nv_fb->nvbo->bo.offset >> 8); evo_mthd(push, 0x0800, 5);
evo_data(push, 0); evo_data(push, nv_fb->nvbo->bo.offset >> 8);
evo_data(push, (fb->height << 16) | fb->width); evo_data(push, 0);
evo_data(push, nv_fb->r_pitch); evo_data(push, (fb->height << 16) | fb->width);
evo_data(push, nv_fb->r_format); evo_data(push, nv_fb->r_pitch);
evo_data(push, nv_fb->r_format);
} else {
evo_mthd(push, 0x0400, 5);
evo_data(push, nv_fb->nvbo->bo.offset >> 8);
evo_data(push, 0);
evo_data(push, (fb->height << 16) | fb->width);
evo_data(push, nv_fb->r_pitch);
evo_data(push, nv_fb->r_format);
}
evo_mthd(push, 0x0080, 1); evo_mthd(push, 0x0080, 1);
evo_data(push, 0x00000000); evo_data(push, 0x00000000);
evo_kick(push, sync); evo_kick(push, sync);