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AT91: trivial: align comment of at91sam9g20_reset with one more tab

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Preparing next patch with longer names

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Nicolas Ferre 2010-10-14 16:51:36 +02:00
parent 184c82e853
commit ef4d63e6f5
1 changed files with 7 additions and 7 deletions
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14
arch/arm/mach-at91/at91sam9g20_reset.S
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@ -33,23 +33,23 @@
.globl at91sam9g20_reset .globl at91sam9g20_reset
at91sam9g20_reset: mov r0, #0 at91sam9g20_reset: mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ flush I-cache mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #CP15_CR_I orr r0, r0, #CP15_CR_I
mcr p15, 0, r0, c1, c0, 0 @ enable I-cache mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
ldr r0, =SDRAMC_BASE @ preload constants ldr r0, =SDRAMC_BASE @ preload constants
ldr r1, =RSTC_BASE ldr r1, =RSTC_BASE
mov r2, #1 mov r2, #1
mov r3, #SDRAMC_LPCB_POWER_DOWN mov r3, #SDRAMC_LPCB_POWER_DOWN
ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
.balign 32 @ align to cache line .balign 32 @ align to cache line
str r2, [r0, #SDRAMC_TR] @ disable SDRAM access str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
str r3, [r0, #SDRAMC_LPR] @ power down SDRAM str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
str r4, [r1, #RSTC_CR] @ reset processor str r4, [r1, #RSTC_CR] @ reset processor
b . b .