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atomic: Delete obsolete documentation
It's been superseded by Documentation/atomic_*.txt. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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=======================================================
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Semantics and Behavior of Atomic and Bitmask Operations
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=======================================================
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:Author: David S. Miller
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This document is intended to serve as a guide to Linux port
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maintainers on how to implement atomic counter, bitops, and spinlock
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interfaces properly.
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Atomic Type And Operations
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==========================
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The atomic_t type should be defined as a signed integer and
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the atomic_long_t type as a signed long integer. Also, they should
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be made opaque such that any kind of cast to a normal C integer type
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will fail. Something like the following should suffice::
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typedef struct { int counter; } atomic_t;
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typedef struct { long counter; } atomic_long_t;
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Historically, counter has been declared volatile. This is now discouraged.
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See :ref:`Documentation/process/volatile-considered-harmful.rst
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<volatile_considered_harmful>` for the complete rationale.
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local_t is very similar to atomic_t. If the counter is per CPU and only
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updated by one CPU, local_t is probably more appropriate. Please see
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:ref:`Documentation/core-api/local_ops.rst <local_ops>` for the semantics of
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local_t.
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The first operations to implement for atomic_t's are the initializers and
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plain writes. ::
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_set(v, i) ((v)->counter = (i))
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The first macro is used in definitions, such as::
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static atomic_t my_counter = ATOMIC_INIT(1);
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The initializer is atomic in that the return values of the atomic operations
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are guaranteed to be correct reflecting the initialized value if the
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initializer is used before runtime. If the initializer is used at runtime, a
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proper implicit or explicit read memory barrier is needed before reading the
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value with atomic_read from another thread.
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As with all of the ``atomic_`` interfaces, replace the leading ``atomic_``
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with ``atomic_long_`` to operate on atomic_long_t.
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The second interface can be used at runtime, as in::
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struct foo { atomic_t counter; };
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...
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struct foo *k;
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k = kmalloc(sizeof(*k), GFP_KERNEL);
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if (!k)
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return -ENOMEM;
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atomic_set(&k->counter, 0);
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The setting is atomic in that the return values of the atomic operations by
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all threads are guaranteed to be correct reflecting either the value that has
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been set with this operation or set with another operation. A proper implicit
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or explicit memory barrier is needed before the value set with the operation
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is guaranteed to be readable with atomic_read from another thread.
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Next, we have::
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#define atomic_read(v) ((v)->counter)
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which simply reads the counter value currently visible to the calling thread.
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The read is atomic in that the return value is guaranteed to be one of the
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values initialized or modified with the interface operations if a proper
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implicit or explicit memory barrier is used after possible runtime
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initialization by any other thread and the value is modified only with the
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interface operations. atomic_read does not guarantee that the runtime
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initialization by any other thread is visible yet, so the user of the
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interface must take care of that with a proper implicit or explicit memory
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barrier.
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.. warning::
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``atomic_read()`` and ``atomic_set()`` DO NOT IMPLY BARRIERS!
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Some architectures may choose to use the volatile keyword, barriers, or
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inline assembly to guarantee some degree of immediacy for atomic_read()
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and atomic_set(). This is not uniformly guaranteed, and may change in
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the future, so all users of atomic_t should treat atomic_read() and
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atomic_set() as simple C statements that may be reordered or optimized
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away entirely by the compiler or processor, and explicitly invoke the
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appropriate compiler and/or memory barrier for each use case. Failure
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to do so will result in code that may suddenly break when used with
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different architectures or compiler optimizations, or even changes in
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unrelated code which changes how the compiler optimizes the section
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accessing atomic_t variables.
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Properly aligned pointers, longs, ints, and chars (and unsigned
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equivalents) may be atomically loaded from and stored to in the same
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sense as described for atomic_read() and atomic_set(). The READ_ONCE()
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and WRITE_ONCE() macros should be used to prevent the compiler from using
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optimizations that might otherwise optimize accesses out of existence on
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the one hand, or that might create unsolicited accesses on the other.
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For example consider the following code::
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while (a > 0)
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do_something();
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If the compiler can prove that do_something() does not store to the
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variable a, then the compiler is within its rights transforming this to
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the following::
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if (a > 0)
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for (;;)
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do_something();
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If you don't want the compiler to do this (and you probably don't), then
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you should use something like the following::
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while (READ_ONCE(a) > 0)
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do_something();
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Alternatively, you could place a barrier() call in the loop.
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For another example, consider the following code::
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tmp_a = a;
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do_something_with(tmp_a);
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do_something_else_with(tmp_a);
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If the compiler can prove that do_something_with() does not store to the
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variable a, then the compiler is within its rights to manufacture an
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additional load as follows::
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tmp_a = a;
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do_something_with(tmp_a);
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tmp_a = a;
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do_something_else_with(tmp_a);
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This could fatally confuse your code if it expected the same value
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to be passed to do_something_with() and do_something_else_with().
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The compiler would be likely to manufacture this additional load if
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do_something_with() was an inline function that made very heavy use
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of registers: reloading from variable a could save a flush to the
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stack and later reload. To prevent the compiler from attacking your
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code in this manner, write the following::
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tmp_a = READ_ONCE(a);
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do_something_with(tmp_a);
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do_something_else_with(tmp_a);
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For a final example, consider the following code, assuming that the
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variable a is set at boot time before the second CPU is brought online
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and never changed later, so that memory barriers are not needed::
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if (a)
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b = 9;
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else
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b = 42;
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The compiler is within its rights to manufacture an additional store
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by transforming the above code into the following::
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b = 42;
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if (a)
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b = 9;
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This could come as a fatal surprise to other code running concurrently
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that expected b to never have the value 42 if a was zero. To prevent
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the compiler from doing this, write something like::
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if (a)
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WRITE_ONCE(b, 9);
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else
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WRITE_ONCE(b, 42);
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Don't even -think- about doing this without proper use of memory barriers,
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locks, or atomic operations if variable a can change at runtime!
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.. warning::
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``READ_ONCE()`` OR ``WRITE_ONCE()`` DO NOT IMPLY A BARRIER!
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Now, we move onto the atomic operation interfaces typically implemented with
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the help of assembly code. ::
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void atomic_add(int i, atomic_t *v);
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void atomic_sub(int i, atomic_t *v);
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void atomic_inc(atomic_t *v);
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void atomic_dec(atomic_t *v);
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These four routines add and subtract integral values to/from the given
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atomic_t value. The first two routines pass explicit integers by
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which to make the adjustment, whereas the latter two use an implicit
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adjustment value of "1".
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One very important aspect of these two routines is that they DO NOT
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require any explicit memory barriers. They need only perform the
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atomic_t counter update in an SMP safe manner.
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Next, we have::
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int atomic_inc_return(atomic_t *v);
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int atomic_dec_return(atomic_t *v);
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These routines add 1 and subtract 1, respectively, from the given
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atomic_t and return the new counter value after the operation is
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performed.
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Unlike the above routines, it is required that these primitives
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include explicit memory barriers that are performed before and after
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the operation. It must be done such that all memory operations before
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and after the atomic operation calls are strongly ordered with respect
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to the atomic operation itself.
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For example, it should behave as if a smp_mb() call existed both
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before and after the atomic operation.
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If the atomic instructions used in an implementation provide explicit
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memory barrier semantics which satisfy the above requirements, that is
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fine as well.
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Let's move on::
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int atomic_add_return(int i, atomic_t *v);
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int atomic_sub_return(int i, atomic_t *v);
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These behave just like atomic_{inc,dec}_return() except that an
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explicit counter adjustment is given instead of the implicit "1".
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This means that like atomic_{inc,dec}_return(), the memory barrier
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semantics are required.
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Next::
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int atomic_inc_and_test(atomic_t *v);
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int atomic_dec_and_test(atomic_t *v);
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These two routines increment and decrement by 1, respectively, the
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given atomic counter. They return a boolean indicating whether the
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resulting counter value was zero or not.
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Again, these primitives provide explicit memory barrier semantics around
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the atomic operation::
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int atomic_sub_and_test(int i, atomic_t *v);
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This is identical to atomic_dec_and_test() except that an explicit
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decrement is given instead of the implicit "1". This primitive must
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provide explicit memory barrier semantics around the operation::
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int atomic_add_negative(int i, atomic_t *v);
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The given increment is added to the given atomic counter value. A boolean
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is return which indicates whether the resulting counter value is negative.
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This primitive must provide explicit memory barrier semantics around
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the operation.
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Then::
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int atomic_xchg(atomic_t *v, int new);
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This performs an atomic exchange operation on the atomic variable v, setting
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the given new value. It returns the old value that the atomic variable v had
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just before the operation.
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atomic_xchg must provide explicit memory barriers around the operation. ::
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int atomic_cmpxchg(atomic_t *v, int old, int new);
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This performs an atomic compare exchange operation on the atomic value v,
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with the given old and new values. Like all atomic_xxx operations,
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atomic_cmpxchg will only satisfy its atomicity semantics as long as all
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other accesses of \*v are performed through atomic_xxx operations.
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atomic_cmpxchg must provide explicit memory barriers around the operation,
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although if the comparison fails then no memory ordering guarantees are
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required.
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The semantics for atomic_cmpxchg are the same as those defined for 'cas'
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below.
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Finally::
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int atomic_add_unless(atomic_t *v, int a, int u);
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If the atomic value v is not equal to u, this function adds a to v, and
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returns non zero. If v is equal to u then it returns zero. This is done as
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an atomic operation.
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atomic_add_unless must provide explicit memory barriers around the
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operation unless it fails (returns 0).
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atomic_inc_not_zero, equivalent to atomic_add_unless(v, 1, 0)
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If a caller requires memory barrier semantics around an atomic_t
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operation which does not return a value, a set of interfaces are
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defined which accomplish this::
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void smp_mb__before_atomic(void);
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void smp_mb__after_atomic(void);
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Preceding a non-value-returning read-modify-write atomic operation with
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smp_mb__before_atomic() and following it with smp_mb__after_atomic()
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provides the same full ordering that is provided by value-returning
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read-modify-write atomic operations.
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For example, smp_mb__before_atomic() can be used like so::
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obj->dead = 1;
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smp_mb__before_atomic();
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atomic_dec(&obj->ref_count);
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It makes sure that all memory operations preceding the atomic_dec()
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call are strongly ordered with respect to the atomic counter
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operation. In the above example, it guarantees that the assignment of
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"1" to obj->dead will be globally visible to other cpus before the
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atomic counter decrement.
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Without the explicit smp_mb__before_atomic() call, the
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implementation could legally allow the atomic counter update visible
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to other cpus before the "obj->dead = 1;" assignment.
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A missing memory barrier in the cases where they are required by the
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atomic_t implementation above can have disastrous results. Here is
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an example, which follows a pattern occurring frequently in the Linux
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kernel. It is the use of atomic counters to implement reference
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counting, and it works such that once the counter falls to zero it can
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be guaranteed that no other entity can be accessing the object::
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static void obj_list_add(struct obj *obj, struct list_head *head)
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{
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obj->active = 1;
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list_add(&obj->list, head);
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}
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static void obj_list_del(struct obj *obj)
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{
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list_del(&obj->list);
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obj->active = 0;
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}
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static void obj_destroy(struct obj *obj)
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{
|
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BUG_ON(obj->active);
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kfree(obj);
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}
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struct obj *obj_list_peek(struct list_head *head)
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{
|
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if (!list_empty(head)) {
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struct obj *obj;
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obj = list_entry(head->next, struct obj, list);
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atomic_inc(&obj->refcnt);
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return obj;
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|
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}
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return NULL;
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}
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void obj_poke(void)
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|
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{
|
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struct obj *obj;
|
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|
|
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spin_lock(&global_list_lock);
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obj = obj_list_peek(&global_list);
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|
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spin_unlock(&global_list_lock);
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|
|
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if (obj) {
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obj->ops->poke(obj);
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|
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if (atomic_dec_and_test(&obj->refcnt))
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|
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obj_destroy(obj);
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|
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}
|
|
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}
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|
||||||
|
|
||||||
void obj_timeout(struct obj *obj)
|
|
||||||
{
|
|
||||||
spin_lock(&global_list_lock);
|
|
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obj_list_del(obj);
|
|
||||||
spin_unlock(&global_list_lock);
|
|
||||||
|
|
||||||
if (atomic_dec_and_test(&obj->refcnt))
|
|
||||||
obj_destroy(obj);
|
|
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}
|
|
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|
|
||||||
.. note::
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|
||||||
|
|
||||||
This is a simplification of the ARP queue management in the generic
|
|
||||||
neighbour discover code of the networking. Olaf Kirch found a bug wrt.
|
|
||||||
memory barriers in kfree_skb() that exposed the atomic_t memory barrier
|
|
||||||
requirements quite clearly.
|
|
||||||
|
|
||||||
Given the above scheme, it must be the case that the obj->active
|
|
||||||
update done by the obj list deletion be visible to other processors
|
|
||||||
before the atomic counter decrement is performed.
|
|
||||||
|
|
||||||
Otherwise, the counter could fall to zero, yet obj->active would still
|
|
||||||
be set, thus triggering the assertion in obj_destroy(). The error
|
|
||||||
sequence looks like this::
|
|
||||||
|
|
||||||
cpu 0 cpu 1
|
|
||||||
obj_poke() obj_timeout()
|
|
||||||
obj = obj_list_peek();
|
|
||||||
... gains ref to obj, refcnt=2
|
|
||||||
obj_list_del(obj);
|
|
||||||
obj->active = 0 ...
|
|
||||||
... visibility delayed ...
|
|
||||||
atomic_dec_and_test()
|
|
||||||
... refcnt drops to 1 ...
|
|
||||||
atomic_dec_and_test()
|
|
||||||
... refcount drops to 0 ...
|
|
||||||
obj_destroy()
|
|
||||||
BUG() triggers since obj->active
|
|
||||||
still seen as one
|
|
||||||
obj->active update visibility occurs
|
|
||||||
|
|
||||||
With the memory barrier semantics required of the atomic_t operations
|
|
||||||
which return values, the above sequence of memory visibility can never
|
|
||||||
happen. Specifically, in the above case the atomic_dec_and_test()
|
|
||||||
counter decrement would not become globally visible until the
|
|
||||||
obj->active update does.
|
|
||||||
|
|
||||||
As a historical note, 32-bit Sparc used to only allow usage of
|
|
||||||
24-bits of its atomic_t type. This was because it used 8 bits
|
|
||||||
as a spinlock for SMP safety. Sparc32 lacked a "compare and swap"
|
|
||||||
type instruction. However, 32-bit Sparc has since been moved over
|
|
||||||
to a "hash table of spinlocks" scheme, that allows the full 32-bit
|
|
||||||
counter to be realized. Essentially, an array of spinlocks are
|
|
||||||
indexed into based upon the address of the atomic_t being operated
|
|
||||||
on, and that lock protects the atomic operation. Parisc uses the
|
|
||||||
same scheme.
|
|
||||||
|
|
||||||
Another note is that the atomic_t operations returning values are
|
|
||||||
extremely slow on an old 386.
|
|
||||||
|
|
||||||
|
|
||||||
Atomic Bitmask
|
|
||||||
==============
|
|
||||||
|
|
||||||
We will now cover the atomic bitmask operations. You will find that
|
|
||||||
their SMP and memory barrier semantics are similar in shape and scope
|
|
||||||
to the atomic_t ops above.
|
|
||||||
|
|
||||||
Native atomic bit operations are defined to operate on objects aligned
|
|
||||||
to the size of an "unsigned long" C data type, and are least of that
|
|
||||||
size. The endianness of the bits within each "unsigned long" are the
|
|
||||||
native endianness of the cpu. ::
|
|
||||||
|
|
||||||
void set_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
void clear_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
void change_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
|
|
||||||
These routines set, clear, and change, respectively, the bit number
|
|
||||||
indicated by "nr" on the bit mask pointed to by "ADDR".
|
|
||||||
|
|
||||||
They must execute atomically, yet there are no implicit memory barrier
|
|
||||||
semantics required of these interfaces. ::
|
|
||||||
|
|
||||||
int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
|
|
||||||
Like the above, except that these routines return a boolean which
|
|
||||||
indicates whether the changed bit was set _BEFORE_ the atomic bit
|
|
||||||
operation.
|
|
||||||
|
|
||||||
|
|
||||||
.. warning::
|
|
||||||
It is incredibly important that the value be a boolean, ie. "0" or "1".
|
|
||||||
Do not try to be fancy and save a few instructions by declaring the
|
|
||||||
above to return "long" and just returning something like "old_val &
|
|
||||||
mask" because that will not work.
|
|
||||||
|
|
||||||
For one thing, this return value gets truncated to int in many code
|
|
||||||
paths using these interfaces, so on 64-bit if the bit is set in the
|
|
||||||
upper 32-bits then testers will never see that.
|
|
||||||
|
|
||||||
One great example of where this problem crops up are the thread_info
|
|
||||||
flag operations. Routines such as test_and_set_ti_thread_flag() chop
|
|
||||||
the return value into an int. There are other places where things
|
|
||||||
like this occur as well.
|
|
||||||
|
|
||||||
These routines, like the atomic_t counter operations returning values,
|
|
||||||
must provide explicit memory barrier semantics around their execution.
|
|
||||||
All memory operations before the atomic bit operation call must be
|
|
||||||
made visible globally before the atomic bit operation is made visible.
|
|
||||||
Likewise, the atomic bit operation must be visible globally before any
|
|
||||||
subsequent memory operation is made visible. For example::
|
|
||||||
|
|
||||||
obj->dead = 1;
|
|
||||||
if (test_and_set_bit(0, &obj->flags))
|
|
||||||
/* ... */;
|
|
||||||
obj->killed = 1;
|
|
||||||
|
|
||||||
The implementation of test_and_set_bit() must guarantee that
|
|
||||||
"obj->dead = 1;" is visible to cpus before the atomic memory operation
|
|
||||||
done by test_and_set_bit() becomes visible. Likewise, the atomic
|
|
||||||
memory operation done by test_and_set_bit() must become visible before
|
|
||||||
"obj->killed = 1;" is visible.
|
|
||||||
|
|
||||||
Finally there is the basic operation::
|
|
||||||
|
|
||||||
int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
|
|
||||||
|
|
||||||
Which returns a boolean indicating if bit "nr" is set in the bitmask
|
|
||||||
pointed to by "addr".
|
|
||||||
|
|
||||||
If explicit memory barriers are required around {set,clear}_bit() (which do
|
|
||||||
not return a value, and thus does not need to provide memory barrier
|
|
||||||
semantics), two interfaces are provided::
|
|
||||||
|
|
||||||
void smp_mb__before_atomic(void);
|
|
||||||
void smp_mb__after_atomic(void);
|
|
||||||
|
|
||||||
They are used as follows, and are akin to their atomic_t operation
|
|
||||||
brothers::
|
|
||||||
|
|
||||||
/* All memory operations before this call will
|
|
||||||
* be globally visible before the clear_bit().
|
|
||||||
*/
|
|
||||||
smp_mb__before_atomic();
|
|
||||||
clear_bit( ... );
|
|
||||||
|
|
||||||
/* The clear_bit() will be visible before all
|
|
||||||
* subsequent memory operations.
|
|
||||||
*/
|
|
||||||
smp_mb__after_atomic();
|
|
||||||
|
|
||||||
There are two special bitops with lock barrier semantics (acquire/release,
|
|
||||||
same as spinlocks). These operate in the same way as their non-_lock/unlock
|
|
||||||
postfixed variants, except that they are to provide acquire/release semantics,
|
|
||||||
respectively. This means they can be used for bit_spin_trylock and
|
|
||||||
bit_spin_unlock type operations without specifying any more barriers. ::
|
|
||||||
|
|
||||||
int test_and_set_bit_lock(unsigned long nr, unsigned long *addr);
|
|
||||||
void clear_bit_unlock(unsigned long nr, unsigned long *addr);
|
|
||||||
void __clear_bit_unlock(unsigned long nr, unsigned long *addr);
|
|
||||||
|
|
||||||
The __clear_bit_unlock version is non-atomic, however it still implements
|
|
||||||
unlock barrier semantics. This can be useful if the lock itself is protecting
|
|
||||||
the other bits in the word.
|
|
||||||
|
|
||||||
Finally, there are non-atomic versions of the bitmask operations
|
|
||||||
provided. They are used in contexts where some other higher-level SMP
|
|
||||||
locking scheme is being used to protect the bitmask, and thus less
|
|
||||||
expensive non-atomic operations may be used in the implementation.
|
|
||||||
They have names similar to the above bitmask operation interfaces,
|
|
||||||
except that two underscores are prefixed to the interface name. ::
|
|
||||||
|
|
||||||
void __set_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
void __clear_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
void __change_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
|
|
||||||
|
|
||||||
These non-atomic variants also do not require any special memory
|
|
||||||
barrier semantics.
|
|
||||||
|
|
||||||
The routines xchg() and cmpxchg() must provide the same exact
|
|
||||||
memory-barrier semantics as the atomic and bit operations returning
|
|
||||||
values.
|
|
||||||
|
|
||||||
.. note::
|
|
||||||
|
|
||||||
If someone wants to use xchg(), cmpxchg() and their variants,
|
|
||||||
linux/atomic.h should be included rather than asm/cmpxchg.h, unless the
|
|
||||||
code is in arch/* and can take care of itself.
|
|
||||||
|
|
||||||
Spinlocks and rwlocks have memory barrier expectations as well.
|
|
||||||
The rule to follow is simple:
|
|
||||||
|
|
||||||
1) When acquiring a lock, the implementation must make it globally
|
|
||||||
visible before any subsequent memory operation.
|
|
||||||
|
|
||||||
2) When releasing a lock, the implementation must make it such that
|
|
||||||
all previous memory operations are globally visible before the
|
|
||||||
lock release.
|
|
||||||
|
|
||||||
Which finally brings us to _atomic_dec_and_lock(). There is an
|
|
||||||
architecture-neutral version implemented in lib/dec_and_lock.c,
|
|
||||||
but most platforms will wish to optimize this in assembler. ::
|
|
||||||
|
|
||||||
int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
|
|
||||||
|
|
||||||
Atomically decrement the given counter, and if will drop to zero
|
|
||||||
atomically acquire the given spinlock and perform the decrement
|
|
||||||
of the counter to zero. If it does not drop to zero, do nothing
|
|
||||||
with the spinlock.
|
|
||||||
|
|
||||||
It is actually pretty simple to get the memory barrier correct.
|
|
||||||
Simply satisfy the spinlock grab requirements, which is make
|
|
||||||
sure the spinlock operation is globally visible before any
|
|
||||||
subsequent memory operation.
|
|
||||||
|
|
||||||
We can demonstrate this operation more clearly if we define
|
|
||||||
an abstract atomic operation::
|
|
||||||
|
|
||||||
long cas(long *mem, long old, long new);
|
|
||||||
|
|
||||||
"cas" stands for "compare and swap". It atomically:
|
|
||||||
|
|
||||||
1) Compares "old" with the value currently at "mem".
|
|
||||||
2) If they are equal, "new" is written to "mem".
|
|
||||||
3) Regardless, the current value at "mem" is returned.
|
|
||||||
|
|
||||||
As an example usage, here is what an atomic counter update
|
|
||||||
might look like::
|
|
||||||
|
|
||||||
void example_atomic_inc(long *counter)
|
|
||||||
{
|
|
||||||
long old, new, ret;
|
|
||||||
|
|
||||||
while (1) {
|
|
||||||
old = *counter;
|
|
||||||
new = old + 1;
|
|
||||||
|
|
||||||
ret = cas(counter, old, new);
|
|
||||||
if (ret == old)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
Let's use cas() in order to build a pseudo-C atomic_dec_and_lock()::
|
|
||||||
|
|
||||||
int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
|
|
||||||
{
|
|
||||||
long old, new, ret;
|
|
||||||
int went_to_zero;
|
|
||||||
|
|
||||||
went_to_zero = 0;
|
|
||||||
while (1) {
|
|
||||||
old = atomic_read(atomic);
|
|
||||||
new = old - 1;
|
|
||||||
if (new == 0) {
|
|
||||||
went_to_zero = 1;
|
|
||||||
spin_lock(lock);
|
|
||||||
}
|
|
||||||
ret = cas(atomic, old, new);
|
|
||||||
if (ret == old)
|
|
||||||
break;
|
|
||||||
if (went_to_zero) {
|
|
||||||
spin_unlock(lock);
|
|
||||||
went_to_zero = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return went_to_zero;
|
|
||||||
}
|
|
||||||
|
|
||||||
Now, as far as memory barriers go, as long as spin_lock()
|
|
||||||
strictly orders all subsequent memory operations (including
|
|
||||||
the cas()) with respect to itself, things will be fine.
|
|
||||||
|
|
||||||
Said another way, _atomic_dec_and_lock() must guarantee that
|
|
||||||
a counter dropping to zero is never made visible before the
|
|
||||||
spinlock being acquired.
|
|
||||||
|
|
||||||
.. note::
|
|
||||||
|
|
||||||
Note that this also means that for the case where the counter is not
|
|
||||||
dropping to zero, there are no memory ordering requirements.
|
|
Loading…
Add table
Reference in a new issue