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pci-v4.13-changes
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Merge tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- add sysfs max_link_speed/width, current_link_speed/width (Wong Vee
Khee)
- make host bridge IRQ mapping much more generic (Matthew Minter,
Lorenzo Pieralisi)
- convert most drivers to pci_scan_root_bus_bridge() (Lorenzo
Pieralisi)
- mutex sriov_configure() (Jakub Kicinski)
- mutex pci_error_handlers callbacks (Christoph Hellwig)
- split ->reset_notify() into ->reset_prepare()/reset_done()
(Christoph Hellwig)
- support multiple PCIe portdrv interrupts for MSI as well as MSI-X
(Gabriele Paoloni)
- allocate MSI/MSI-X vector for Downstream Port Containment (Gabriele
Paoloni)
- fix MSI IRQ affinity pre/post/min_vecs issue (Michael Hernandez)
- test INTx masking during enumeration, not at run-time (Piotr Gregor)
- avoid using device_may_wakeup() for runtime PM (Rafael J. Wysocki)
- restore the status of PCI devices across hibernation (Chen Yu)
- keep parent resources that start at 0x0 (Ard Biesheuvel)
- enable ECRC only if device supports it (Bjorn Helgaas)
- restore PRI and PASID state after Function-Level Reset (CQ Tang)
- skip DPC event if device is not present (Keith Busch)
- check domain when matching SMBIOS info (Sujith Pandel)
- mark Intel XXV710 NIC INTx masking as broken (Alex Williamson)
- avoid AMD SB7xx EHCI USB wakeup defect (Kai-Heng Feng)
- work around long-standing Macbook Pro poweroff issue (Bjorn Helgaas)
- add Switchtec "running" status flag (Logan Gunthorpe)
- fix dra7xx incorrect RW1C IRQ register usage (Arvind Yadav)
- modify xilinx-nwl IRQ chip for legacy interrupts (Bharat Kumar
Gogada)
- move VMD SRCU cleanup after bus, child device removal (Jon Derrick)
- add Faraday clock handling (Linus Walleij)
- configure Rockchip MPS and reorganize (Shawn Lin)
- limit Qualcomm TLP size to 2K (hardware issue) (Srinivas Kandagatla)
- support Tegra MSI 64-bit addressing (Thierry Reding)
- use Rockchip normal (not privileged) register bank (Shawn Lin)
- add HiSilicon Kirin SoC PCIe controller driver (Xiaowei Song)
- add Sigma Designs Tango SMP8759 PCIe controller driver (Marc
Gonzalez)
- add MediaTek PCIe host controller support (Ryder Lee)
- add Qualcomm IPQ4019 support (John Crispin)
- add HyperV vPCI protocol v1.2 support (Jork Loeser)
- add i.MX6 regulator support (Quentin Schulz)
* tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (113 commits)
PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support
PCI: Add DT binding for Sigma Designs Tango PCIe controller
PCI: rockchip: Use normal register bank for config accessors
dt-bindings: PCI: Add documentation for MediaTek PCIe
PCI: Remove __pci_dev_reset() and pci_dev_reset()
PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()
PCI: xilinx: Make of_device_ids const
PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts
PCI: vmd: Move SRCU cleanup after bus, child device removal
PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000
PCI: versatile: Add local struct device pointers
PCI: tegra: Do not allocate MSI target memory
PCI: tegra: Support MSI 64-bit addressing
PCI: rockchip: Use local struct device pointer consistently
PCI: rockchip: Check for clk_prepare_enable() errors during resume
MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer
PCI: rockchip: Configure RC's MPS setting
PCI: rockchip: Reconfigure configuration space header type
PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()
PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()
...
This commit is contained in:
Linus Torvalds
commit
f263fbb8d6
90 changed files with 3789 additions and 825 deletions
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@ -360,6 +360,8 @@ struct pci_dev {
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unsigned int msix_enabled:1;
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unsigned int ari_enabled:1; /* ARI forwarding */
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unsigned int ats_enabled:1; /* Address Translation Service */
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unsigned int pasid_enabled:1; /* Process Address Space ID */
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unsigned int pri_enabled:1; /* Page Request Interface */
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unsigned int is_managed:1;
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unsigned int needs_freset:1; /* Dev requires fundamental reset */
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unsigned int state_saved:1;
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@ -370,7 +372,7 @@ struct pci_dev {
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unsigned int is_thunderbolt:1; /* Thunderbolt controller */
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unsigned int __aer_firmware_first_valid:1;
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unsigned int __aer_firmware_first:1;
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unsigned int broken_intx_masking:1;
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unsigned int broken_intx_masking:1; /* INTx masking can't be used */
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unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
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unsigned int irq_managed:1;
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unsigned int has_secondary_link:1;
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@ -403,6 +405,12 @@ struct pci_dev {
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u16 ats_cap; /* ATS Capability offset */
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u8 ats_stu; /* ATS Smallest Translation Unit */
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atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
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#endif
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#ifdef CONFIG_PCI_PRI
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u32 pri_reqs_alloc; /* Number of PRI requests allocated */
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#endif
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#ifdef CONFIG_PCI_PASID
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u16 pasid_features;
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#endif
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phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
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size_t romlen; /* Length of ROM if it's not from the BAR */
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@ -437,6 +445,8 @@ struct pci_host_bridge {
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void *sysdata;
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int busnr;
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struct list_head windows; /* resource_entry */
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u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
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int (*map_irq)(const struct pci_dev *, u8, u8);
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void (*release_fn)(struct pci_host_bridge *);
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void *release_data;
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struct msi_controller *msi;
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@ -463,7 +473,9 @@ static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
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}
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struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
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int pci_register_host_bridge(struct pci_host_bridge *bridge);
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struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
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size_t priv);
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void pci_free_host_bridge(struct pci_host_bridge *bridge);
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struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
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void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
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@ -695,7 +707,8 @@ struct pci_error_handlers {
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pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
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/* PCI function reset prepare or completed */
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void (*reset_notify)(struct pci_dev *dev, bool prepare);
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void (*reset_prepare)(struct pci_dev *dev);
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void (*reset_done)(struct pci_dev *dev);
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/* Device driver may resume normal operations */
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void (*resume)(struct pci_dev *dev);
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@ -852,13 +865,10 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
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int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
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int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
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void pci_bus_release_busn_res(struct pci_bus *b);
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struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
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struct pci_ops *ops, void *sysdata,
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struct list_head *resources,
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struct msi_controller *msi);
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struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
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struct pci_ops *ops, void *sysdata,
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struct list_head *resources);
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int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
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struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
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int busnr);
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void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
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@ -1008,6 +1018,15 @@ int __must_check pci_reenable_device(struct pci_dev *);
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int __must_check pcim_enable_device(struct pci_dev *pdev);
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void pcim_pin_device(struct pci_dev *pdev);
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static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
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{
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/*
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* INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
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* writable and no quirk has marked the feature broken.
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*/
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return !pdev->broken_intx_masking;
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}
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static inline int pci_is_enabled(struct pci_dev *pdev)
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{
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return (atomic_read(&pdev->enable_cnt) > 0);
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@ -1031,7 +1050,6 @@ int __must_check pci_set_mwi(struct pci_dev *dev);
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int pci_try_set_mwi(struct pci_dev *dev);
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void pci_clear_mwi(struct pci_dev *dev);
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void pci_intx(struct pci_dev *dev, int enable);
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bool pci_intx_mask_supported(struct pci_dev *dev);
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bool pci_check_and_mask_intx(struct pci_dev *dev);
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bool pci_check_and_unmask_intx(struct pci_dev *dev);
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int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
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@ -1144,6 +1162,7 @@ void pdev_enable_device(struct pci_dev *);
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int pci_enable_resources(struct pci_dev *, int mask);
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void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
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int (*)(const struct pci_dev *, u8, u8));
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void pci_assign_irq(struct pci_dev *dev);
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struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
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#define HAVE_PCI_REQ_REGIONS 2
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int __must_check pci_request_regions(struct pci_dev *, const char *);
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