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Renesas ARM DT updates for v5.13

Browse source 
- OV7725 camera support for the iWave RainboW Qseven board (G21D), and
     its camera expansion board,
   - Add mmc aliases to fix /dev/mmcblkN order,
   - HDMI Display support for the R-Car Starter Kit Pro with R-Car M3-W+,
   - Support for running upstream kernels on the RZA2MEVB board, using
     the SDRAM present on the sub-board,
   - I2C EEPROM support for the Falcon development board,
   - Timer, thermal sensor, and CAN support for the R-Car V3U SoC.
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.13

  - OV7725 camera support for the iWave RainboW Qseven board (G21D), and
    its camera expansion board,
  - Add mmc aliases to fix /dev/mmcblkN order,
  - HDMI Display support for the R-Car Starter Kit Pro with R-Car M3-W+,
  - Support for running upstream kernels on the RZA2MEVB board, using
    the SDRAM present on the sub-board,
  - I2C EEPROM support for the Falcon development board,
  - Timer, thermal sensor, and CAN support for the R-Car V3U SoC.
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a77980: Fix vin4-7 endpoint binding
  arm64: dts: renesas: r8a77961: Add CAN nodes
  arm64: dts: renesas: r8a779a0: Add CMT support
  arm64: dts: renesas: r8a779a0: Add thermal support
  arm64: dts: renesas: r8a779a0: Add TMU support
  arm64: dts: renesas: falcon: Add Ethernet sub-board
  arm64: dts: renesas: falcon: Add CSI/DSI sub-board
  arm64: dts: renesas: falcon: Add I2C EEPROM nodes
  ARM: dts: rza2mevb: Upstream Linux requires SDRAM
  arm64: dts: renesas: Consolidate Salvator-X(S) HDMI0 handling
  arm64: dts: renesas: Add mmc aliases into board dts files
  arm64: dts: renesas: r8a77961-ulcb: add HDMI Display support
  ARM: dts: renesas: Add mmc aliases into R-Car Gen2 board dts files
  arm64: dts: renesas: Group tuples in pin control properties
  arm64: dts: renesas: Group tuples in playback and capture properties
  ARM: dts: renesas: Group tuples in pin control properties
  ARM: dts: renesas: Group tuples in playback and capture properties
  ARM: dts: renesas: Group tuples in APMU cpus properties
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes

Link: https://lore.kernel.org/r/20210319085146.2709844-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-03-23 18:22:41 +01:00
commit f38dc82b56
55 changed files with 617 additions and 504 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/boot/dts/iwg20d-q7-common.dtsi
View file

@ -325,8 +325,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi1 &src3 &dvc1>;
capture = <&ssi0 &src2 &dvc0>;
playback = <&ssi1>, <&src3>, <&dvc1>;
capture = <&ssi0>, <&src2>, <&dvc0>;
};
};
};

55
arch/arm/boot/dts/r7s9210-rza2mevb.dts
View file

@ -4,6 +4,28 @@
*
* Copyright (C) 2018 Renesas Electronics
*
* As upstream Linux does not support XIP, it cannot run in 8 MiB of HyperRAM.
* Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
* the following ramifications:
* - SCIF4 connected to the on-board USB-serial can no longer be used as the
* serial console,
* - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL
* USB-to-Serial adapter to the CMOS camera connector:
* - RXD = CN17-9,
* - TXD = CN17-10,
* - GND = CN17-2 or CN17-17,
* - The first Ethernet channel can no longer be used,
* - USB Channel 1 loses the overcurrent input signal.
*
* Please make sure your sub-board matches the following switch settings:
*
* SW6 SW6-1 set to SDRAM
* ON SW6-2 set to Audio
* +---------------------+ SW6-3 set to DRP
* | = = = = = | SW6-4 set to CEU
* | = = | SW6-5 set to Ether2
* | 1 2 3 4 5 6 7 8 9 0 | SW6-6 set to VDC6
* +---------------------+ SW6-7 set to VDC6
*/
/dts-v1/;
@ -17,9 +39,8 @@
compatible = "renesas,rza2mevb", "renesas,r7s9210";
aliases {
serial0 = &scif4;
ethernet0 = &ether0;
ethernet1 = &ether1;
serial0 = &scif2;
ethernet0 = &ether1;
};
chosen {
@ -58,9 +79,9 @@
};
};
memory@40000000 {
memory@c000000 {
device_type = "memory";
reg = <0x40000000 0x00800000>; /* HyperRAM */
reg = <0x0c000000 0x04000000>; /* SDRAM */
};
};
@ -72,17 +93,6 @@
status = "okay";
};
&ether0 {
pinctrl-names = "default";
pinctrl-0 = <&eth0_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&ether1 {
pinctrl-names = "default";
pinctrl-0 = <&eth1_pins>;
@ -142,9 +152,9 @@
};
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
scif2_pins: serial2 {
pinmux = <RZA2_PINMUX(PORTE, 2, 3)>, /* TxD2 */
<RZA2_PINMUX(PORTE, 1, 3)>; /* RxD2 */
};
sdhi0_pins: sdhi0 {
@ -165,8 +175,7 @@
usb1_pins: usb1 {
pinmux = <RZA2_PINMUX(PORTC, 0, 1)>, /* VBUSIN1 */
<RZA2_PINMUX(PORTC, 5, 1)>, /* VBUSEN1 */
<RZA2_PINMUX(PORT7, 5, 5)>; /* OVRCUR1 */
<RZA2_PINMUX(PORTC, 5, 1)>; /* VBUSEN1 */
};
};
@ -176,9 +185,9 @@
};
/* Serial Console */
&scif4 {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif4_pins>;
pinctrl-0 = <&scif2_pins>;
status = "okay";
};

155
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
View file

@ -91,92 +91,20 @@
status = "okay";
};
&i2c0 {
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam1>;
clock-names = "xclk";
port {
ov5640_0: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin0ep>;
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
/* status set to "okay" when needed by camera configuration below */
clock-frequency = <400000>;
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam2>;
clock-names = "xclk";
port {
ov5640_1: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin1ep>;
};
};
};
};
&i2c2 {
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam3>;
clock-names = "xclk";
port {
ov5640_2: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin2ep>;
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
/* status set to "okay" when needed by camera configuration below */
clock-frequency = <400000>;
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam4>;
clock-names = "xclk";
port {
ov5640_3: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin3ep>;
};
};
};
};
&pfc {
@ -267,6 +195,22 @@
cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
};
/*
* Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints
*
* (un)comment the #include statements to change configuration
*/
/* 8bit CMOS Camera 1 (J13) */
#define CAM_PARENT_I2C i2c0
#define MCLK_CAM mclk_cam1
#define CAM_EP cam0ep
#define VIN_EP vin0ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
#ifdef CAM_ENABLED
&vin0 {
/*
* Set SW2 switch on the SOM to 'ON'
@ -278,13 +222,29 @@
port {
vin0ep: endpoint {
remote-endpoint = <&ov5640_0>;
remote-endpoint = <&cam0ep>;
bus-width = <8>;
bus-type = <6>;
};
};
};
#endif /* CAM_ENABLED */
#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP
/* 8bit CMOS Camera 2 (J14) */
#define CAM_PARENT_I2C i2c1
#define MCLK_CAM mclk_cam2
#define CAM_EP cam1ep
#define VIN_EP vin1ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
#ifdef CAM_ENABLED
&vin1 {
/* Set SW1 switch on the SOM to 'ON' */
status = "okay";
@ -293,13 +253,30 @@
port {
vin1ep: endpoint {
remote-endpoint = <&ov5640_1>;
remote-endpoint = <&cam1ep>;
bus-width = <8>;
bus-type = <6>;
};
};
};
#endif /* CAM_ENABLED */
#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP
/* 8bit CMOS Camera 3 (J12) */
#define CAM_PARENT_I2C i2c2
#define MCLK_CAM mclk_cam3
#define CAM_EP cam2ep
#define VIN_EP vin2ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
#ifdef CAM_ENABLED
&vin2 {
status = "okay";
pinctrl-0 = <&vin2_pins>;
@ -307,14 +284,30 @@
port {
vin2ep: endpoint {
remote-endpoint = <&ov5640_2>;
remote-endpoint = <&cam2ep>;
bus-width = <8>;
data-shift = <8>;
bus-type = <6>;
};
};
};
#endif /* CAM_ENABLED */
#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP
/* 8bit CMOS Camera 4 (J11) */
#define CAM_PARENT_I2C i2c3
#define MCLK_CAM mclk_cam4
#define CAM_EP cam3ep
#define VIN_EP vin3ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
#ifdef CAM_ENABLED
&vin3 {
status = "okay";
pinctrl-0 = <&vin3_pins>;
@ -322,9 +315,15 @@
port {
vin3ep: endpoint {
remote-endpoint = <&ov5640_3>;
remote-endpoint = <&cam3ep>;
bus-width = <8>;
bus-type = <6>;
};
};
};
#endif /* CAM_ENABLED */
#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP

32
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi Normal file
View file

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This include file ties a VIN interface with a single ov5640 sensor on
* the iWave-RZ/G1H Qseven board development platform connected with the
* camera daughter board.
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#define CAM_ENABLED 1
&CAM_PARENT_I2C {
status = "okay";
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&MCLK_CAM>;
clock-names = "xclk";
status = "okay";
port {
CAM_EP: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&VIN_EP>;
};
};
};
};

29
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi Normal file
View file

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This include file ties a VIN interface with a single ov7725 sensor on
* the iWave-RZ/G1H Qseven board development platform connected with the
* camera daughter board.
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#define CAM_ENABLED 1
&CAM_PARENT_I2C {
status = "okay";
ov7725@21 {
compatible = "ovti,ov7725";
reg = <0x21>;
clocks = <&MCLK_CAM>;
status = "okay";
port {
CAM_EP: endpoint {
bus-width = <8>;
bus-type = <6>;
remote-endpoint = <&VIN_EP>;
};
};
};
};

4
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
View file

@ -387,8 +387,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi4 &src4 &dvc1>;
capture = <&ssi3 &src3 &dvc0>;
playback = <&ssi4>, <&src4>, <&dvc1>;
capture = <&ssi3>, <&src3>, <&dvc0>;
};
};
};

4
arch/arm/boot/dts/r8a7742.dtsi
View file

@ -367,13 +367,13 @@
apmu@e6151000 {
compatible = "renesas,r8a7742-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
apmu@e6152000 {
compatible = "renesas,r8a7742-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
rst: reset-controller@e6160000 {

2
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
View file

@ -61,7 +61,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;

2
arch/arm/boot/dts/r8a7743.dtsi
View file

@ -293,7 +293,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7743-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

2
arch/arm/boot/dts/r8a7744.dtsi
View file

@ -293,7 +293,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7744-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

4
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
View file

@ -289,8 +289,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi3 &src3 &dvc0>;
capture = <&ssi4 &src4 &dvc1>;
playback = <&ssi3>, <&src3>, <&dvc0>;
capture = <&ssi4>, <&src4>, <&dvc1>;
};
};
};

2
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
View file

@ -56,7 +56,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;

2
arch/arm/boot/dts/r8a7745.dtsi
View file

@ -258,7 +258,7 @@
apmu@e6151000 {
compatible = "renesas,r8a7745-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

2
arch/arm/boot/dts/r8a77470.dtsi
View file

@ -205,7 +205,7 @@
apmu@e6151000 {
compatible = "renesas,r8a77470-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

11
arch/arm/boot/dts/r8a7790-lager.dts
View file

@ -53,6 +53,9 @@
i2c11 = &i2cexio1;
i2c12 = &i2chdmi;
i2c13 = &i2cpwr;
mmc0 = &mmcif1;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
@ -659,7 +662,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -908,7 +911,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -918,8 +921,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

4
arch/arm/boot/dts/r8a7790-stout.dts
View file

@ -191,7 +191,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -321,7 +321,7 @@
&iic3 {
pinctrl-names = "default";
pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>;
status = "okay";
pmic@58 {

4
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -381,13 +381,13 @@
apmu@e6151000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
apmu@e6152000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
rst: reset-controller@e6160000 {

11
arch/arm/boot/dts/r8a7791-koelsch.dts
View file

@ -53,6 +53,9 @@
i2c12 = &i2cexio1;
i2c13 = &i2chdmi;
i2c14 = &i2cexio4;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
mmc2 = &sdhi2;
};
chosen {
@ -618,7 +621,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -878,7 +881,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -888,8 +891,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

6
arch/arm/boot/dts/r8a7791-porter.dts
View file

@ -28,6 +28,8 @@
serial0 = &scif0;
i2c9 = &gpioi2c2;
i2c10 = &i2chdmi;
mmc0 = &sdhi0;
mmc1 = &sdhi2;
};
chosen {
@ -292,7 +294,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -494,7 +496,7 @@
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
pinctrl-names = "default";
status = "okay";

2
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -315,7 +315,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

2
arch/arm/boot/dts/r8a7792-blanche.dts
View file

@ -334,7 +334,7 @@
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-0 = <&du0_pins>, <&du1_pins>;
pinctrl-names = "default";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;

2
arch/arm/boot/dts/r8a7792-wheat.dts
View file

@ -307,7 +307,7 @@
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-0 = <&du0_pins>, <&du1_pins>;
pinctrl-names = "default";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>;

2
arch/arm/boot/dts/r8a7792.dtsi
View file

@ -314,7 +314,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

11
arch/arm/boot/dts/r8a7793-gose.dts
View file

@ -49,6 +49,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
mmc2 = &sdhi2;
};
chosen {
@ -576,7 +579,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -751,7 +754,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -761,8 +764,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

2
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -290,7 +290,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7793-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

5
arch/arm/boot/dts/r8a7794-alt.dts
View file

@ -19,6 +19,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
mmc0 = &mmcif0;
mmc1 = &sdhi0;
mmc2 = &sdhi1;
};
chosen {
@ -330,7 +333,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;

8
arch/arm/boot/dts/r8a7794-silk.dts
View file

@ -31,6 +31,8 @@
serial0 = &scif2;
i2c9 = &gpioi2c1;
i2c10 = &i2chdmi;
mmc0 = &mmcif0;
mmc1 = &sdhi1;
};
chosen {
@ -379,7 +381,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -518,7 +520,7 @@
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-0 = <&du0_pins>, <&du1_pins>;
pinctrl-names = "default";
status = "okay";
@ -541,7 +543,7 @@
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
pinctrl-names = "default";
status = "okay";

2
arch/arm/boot/dts/r8a7794.dtsi
View file

@ -256,7 +256,7 @@
apmu@e6151000 {
compatible = "renesas,r8a7794-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {

4
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View file

@ -615,7 +615,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -639,7 +639,7 @@
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi1 &dvc1 &src1>;
playback = <&ssi1>, <&dvc1>, <&src1>;
capture = <&ssi0>;
};
};

3
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View file

@ -12,6 +12,9 @@
aliases {
serial0 = &scif2;
serial1 = &hscif0;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {

2
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View file

@ -80,7 +80,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";

3
arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
View file

@ -21,6 +21,9 @@
serial4 = &hscif2;
serial5 = &scif5;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {

3
arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts
View file

@ -22,6 +22,9 @@
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {

6
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
View file

@ -17,6 +17,8 @@
aliases {
serial0 = &scif2;
serial1 = &hscif2;
mmc0 = &sdhi0;
mmc1 = &sdhi3;
};
chosen {
@ -351,7 +353,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -365,7 +367,7 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
playback = <&ssi0>, <&src0>, <&dvc0>;
};
};
};

3
arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts
View file

@ -22,6 +22,9 @@
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {

37
arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts
View file

@ -52,29 +52,6 @@
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&hdmi1 {
status = "okay";
@ -111,19 +88,7 @@
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
/* rsnd_port0/1 are described in salvator-common.dtsi */
rsnd_port2: port@2 {
reg = <2>;
rsnd_endpoint2: endpoint {

37
arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts
View file

@ -52,29 +52,6 @@
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&hdmi1 {
status = "okay";
@ -111,19 +88,7 @@
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
/* rsnd_port0/1 are described in salvator-common.dtsi */
rsnd_port2: port@2 {
reg = <2>;
rsnd_endpoint2: endpoint {

37
arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts
View file

@ -57,29 +57,6 @@
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&hdmi1 {
status = "okay";
@ -152,19 +129,7 @@
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
/* rsnd_port0/1 are described in salvator-common.dtsi */
rsnd_port2: port@2 {
reg = <2>;
rsnd_endpoint2: endpoint {

46
arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts
View file

@ -35,49 +35,3 @@
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

46
arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts
View file

@ -35,49 +35,3 @@
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

46
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
View file

@ -40,49 +40,3 @@
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

11
arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts
View file

@ -30,3 +30,14 @@
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};

26
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file

@ -1155,13 +1155,35 @@
};
can0: can@e6c30000 {
compatible = "renesas,can-r8a77961",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
/* placeholder */
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77961_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a77961",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
/* placeholder */
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A77961_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
pwm0: pwm@e6e30000 {

45
arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
View file

@ -30,48 +30,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

45
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
View file

@ -31,29 +31,6 @@
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&pca9654 {
pcie-sata-switch-hog {
gpio-hog;
@ -63,29 +40,7 @@
};
};
&rcar_sound {
ports {
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
&sata {
status = "okay";
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

16
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file

@ -992,8 +992,8 @@
reg = <1>;
vin4csi41: endpoint@2 {
reg = <2>;
vin4csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin4>;
};
};
@ -1020,8 +1020,8 @@
reg = <1>;
vin5csi41: endpoint@2 {
reg = <2>;
vin5csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin5>;
};
};
@ -1048,8 +1048,8 @@
reg = <1>;
vin6csi41: endpoint@2 {
reg = <2>;
vin6csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin6>;
};
};
@ -1076,8 +1076,8 @@
reg = <1>;
vin7csi41: endpoint@2 {
reg = <2>;
vin7csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin7>;
};
};

9
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View file

@ -16,6 +16,9 @@
aliases {
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi1;
};
chosen {
@ -621,7 +624,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -653,8 +656,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};

7
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
View file

@ -82,6 +82,13 @@
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {

15
arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CSI/DSI sub-board
*
* Copyright (C) 2021 Glider bv
*/
&i2c0 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
};

15
arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon Ethernet sub-board
*
* Copyright (C) 2021 Glider bv
*/
&i2c0 {
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};

11
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
View file

@ -7,6 +7,8 @@
/dts-v1/;
#include "r8a779a0-falcon-cpu.dtsi"
#include "r8a779a0-falcon-csi-dsi.dtsi"
#include "r8a779a0-falcon-ethernet.dtsi"
/ {
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
@ -22,6 +24,15 @@
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

220
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file

@ -239,6 +239,76 @@
#interrupt-cells = <2>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a779a0-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 910>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 910>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a779a0-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 911>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 911>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a779a0-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 912>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 912>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a779a0-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 913>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 913>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
@ -260,6 +330,84 @@
#power-domain-cells = <1>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 714>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
tsc: thermal@e6190000 {
compatible = "renesas,r8a779a0-thermal";
reg = <0 0xe6190000 0 0x200>,
<0 0xe6198000 0 0x200>,
<0 0xe61a0000 0 0x200>,
<0 0xe61a8000 0 0x200>,
<0 0xe61b0000 0 0x200>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 919>;
#thermal-sensor-cells = <1>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
@ -960,6 +1108,78 @@
};
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
trips {
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal4: sensor-thermal4 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 3>;
trips {
sensor4_crit: sensor4-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal5: sensor-thermal5 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 4>;
trips {
sensor5_crit: sensor5-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

48
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file

@ -36,6 +36,9 @@
serial0 = &scif2;
serial1 = &hscif1;
ethernet0 = &avb;
mmc0 = &sdhi2;
mmc1 = &sdhi0;
mmc2 = &sdhi3;
};
chosen {
@ -198,7 +201,8 @@
label = "rcar-sound";
dais = <&rsnd_port0>;
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};
vbus0_usb2: regulator-vbus0-usb2 {
@ -394,6 +398,29 @@
clock-frequency = <32768>;
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
@ -730,7 +757,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -773,8 +800,21 @@
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};

1
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View file

@ -16,6 +16,7 @@
aliases {
serial1 = &hscif0;
serial2 = &scif1;
mmc2 = &sdhi3;
};
clksndsel: clksndsel {

8
arch/arm64/boot/dts/renesas/ulcb.dtsi
View file

@ -23,6 +23,8 @@
aliases {
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi2;
mmc1 = &sdhi0;
};
chosen {
@ -365,7 +367,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -408,8 +410,8 @@
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
rsnd_port1: port@1 {