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powerpc/watchpoint: Fix DAWR exception for CACHEOP
'ea' returned by analyse_instr() needs to be aligned down to cache block size for CACHEOP instructions. analyse_instr() does not set size for CACHEOP, thus size also needs to be calculated manually. Fixes:27985b2a64
("powerpc/watchpoint: Don't ignore extraneous exceptions blindly") Fixes:74c6881019
("powerpc/watchpoint: Prepare handler to handle more than one watchpoint") Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200723090813.303838-4-ravi.bangoria@linux.ibm.com
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1 changed files with 20 additions and 1 deletions
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@ -538,7 +538,12 @@ static bool check_dawrx_constraints(struct pt_regs *regs, int type,
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if (OP_IS_LOAD(type) && !(info->type & HW_BRK_TYPE_READ))
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return false;
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if (OP_IS_STORE(type) && !(info->type & HW_BRK_TYPE_WRITE))
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/*
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* The Cache Management instructions other than dcbz never
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* cause a match. i.e. if type is CACHEOP, the instruction
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* is dcbz, and dcbz is treated as Store.
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*/
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if ((OP_IS_STORE(type) || type == CACHEOP) && !(info->type & HW_BRK_TYPE_WRITE))
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return false;
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if (is_kernel_addr(regs->nip) && !(info->type & HW_BRK_TYPE_KERNEL))
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@ -601,6 +606,15 @@ static bool check_constraints(struct pt_regs *regs, struct ppc_inst instr,
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return false;
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}
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static int cache_op_size(void)
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{
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#ifdef __powerpc64__
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return ppc64_caches.l1d.block_size;
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#else
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return L1_CACHE_BYTES;
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#endif
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}
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static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
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int *type, int *size, unsigned long *ea)
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{
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@ -616,7 +630,12 @@ static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
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if (!(regs->msr & MSR_64BIT))
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*ea &= 0xffffffffUL;
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#endif
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*size = GETSIZE(op.type);
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if (*type == CACHEOP) {
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*size = cache_op_size();
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*ea &= ~(*size - 1);
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}
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}
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static bool is_larx_stcx_instr(int type)
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