mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-06-20 13:41:30 +00:00
Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next
- Remove clk_readl() and introduce BE versions of basic clk types
* clk-doc:
clk: Drop duplicate clk_register() documentation
clk: Document and simplify clk_core_get_rate_nolock()
clk: Remove 'flags' member of struct clk_fixed_rate
clk: nxp: Drop 'flags' on fixed_rate clk macro
clk: Document __clk_mux_determine_rate()
clk: Document CLK_MUX_READ_ONLY mux flag
clk: Document deprecated things
clk: Collapse gpio clk kerneldoc
* clk-more-critical:
clk: highbank: Convert to CLK_IS_CRITICAL
* clk-meson: (21 commits)
clk: meson: axg-audio: add g12a support
clk: meson: axg-audio: don't register inputs in the onecell data
clk: meson: axg_audio: replace prefix axg by aud
dt-bindings: clk: axg-audio: add g12a support
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
dt-bindings: clock: meson8b: export the video decoder clocks
clk: meson-g12a: add video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
clk: meson-g12a: add PCIE PLL clocks
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
dt-bindings: clock: meson8b: drop the "ABP" clock definition
clk: meson: g12a: add cpu clocks
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
...
* clk-basic-be:
clk: core: replace clk_{readl,writel} with {readl,writel}
clk: core: remove powerpc special handling
powerpc/512x: mark clocks as big endian
clk: mux: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: gate: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: divider: add explicit big endian support
This commit is contained in:
Stephen Boyd
commit
f6111b9d79
36 changed files with 2399 additions and 685 deletions
|
|
@ -24,7 +24,7 @@
|
|||
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
|
||||
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
|
||||
/* unused */
|
||||
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
|
||||
#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */
|
||||
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
|
||||
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
|
||||
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
|
||||
|
|
@ -307,7 +307,6 @@ struct clk_fixed_rate {
|
|||
struct clk_hw hw;
|
||||
unsigned long fixed_rate;
|
||||
unsigned long fixed_accuracy;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
|
@ -349,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np);
|
|||
* of this register, and mask of gate bits are in higher 16-bit of this
|
||||
* register. While setting the gate bits, higher 16-bit should also be
|
||||
* updated to indicate changing gate bits.
|
||||
* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
|
||||
* the gate register. Setting this flag makes the register accesses big
|
||||
* endian.
|
||||
*/
|
||||
struct clk_gate {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -362,6 +364,7 @@ struct clk_gate {
|
|||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
#define CLK_GATE_HIWORD_MASK BIT(1)
|
||||
#define CLK_GATE_BIG_ENDIAN BIT(2)
|
||||
|
||||
extern const struct clk_ops clk_gate_ops;
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
|
|
@ -417,6 +420,9 @@ struct clk_div_table {
|
|||
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
|
||||
* except when the value read from the register is zero, the divisor is
|
||||
* 2^width of the field.
|
||||
* CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
|
||||
* for the divider register. Setting this flag makes the register accesses
|
||||
* big endian.
|
||||
*/
|
||||
struct clk_divider {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -438,6 +444,7 @@ struct clk_divider {
|
|||
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
|
||||
#define CLK_DIVIDER_READ_ONLY BIT(5)
|
||||
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
|
||||
#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
|
||||
|
||||
extern const struct clk_ops clk_divider_ops;
|
||||
extern const struct clk_ops clk_divider_ro_ops;
|
||||
|
|
@ -499,8 +506,13 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
|
|||
* register, and mask of mux bits are in higher 16-bit of this register.
|
||||
* While setting the mux bits, higher 16-bit should also be updated to
|
||||
* indicate changing mux bits.
|
||||
* CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
|
||||
* .get_parent clk_op.
|
||||
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
|
||||
* frequency.
|
||||
* CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
|
||||
* the mux register. Setting this flag makes the register accesses big
|
||||
* endian.
|
||||
*/
|
||||
struct clk_mux {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -519,6 +531,7 @@ struct clk_mux {
|
|||
#define CLK_MUX_HIWORD_MASK BIT(2)
|
||||
#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
|
||||
#define CLK_MUX_ROUND_CLOSEST BIT(4)
|
||||
#define CLK_MUX_BIG_ENDIAN BIT(5)
|
||||
|
||||
extern const struct clk_ops clk_mux_ops;
|
||||
extern const struct clk_ops clk_mux_ro_ops;
|
||||
|
|
@ -602,6 +615,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
|
|||
* is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
|
||||
* is set then the numerator and denominator are both the value read
|
||||
* plus one.
|
||||
* CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
|
||||
* used for the divider register. Setting this flag makes the register
|
||||
* accesses big endian.
|
||||
*/
|
||||
struct clk_fractional_divider {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -622,6 +638,7 @@ struct clk_fractional_divider {
|
|||
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
|
||||
|
||||
#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
|
||||
#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
|
||||
|
||||
extern const struct clk_ops clk_fractional_divider_ops;
|
||||
struct clk *clk_register_fractional_divider(struct device *dev,
|
||||
|
|
@ -654,6 +671,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
|
|||
* leaving the parent rate unmodified.
|
||||
* CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
|
||||
* rounded to the closest integer instead of the down one.
|
||||
* CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
|
||||
* used for the multiplier register. Setting this flag makes the register
|
||||
* accesses big endian.
|
||||
*/
|
||||
struct clk_multiplier {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -668,6 +688,7 @@ struct clk_multiplier {
|
|||
|
||||
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
|
||||
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
|
||||
#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
|
||||
|
||||
extern const struct clk_ops clk_multiplier_ops;
|
||||
|
||||
|
|
@ -712,16 +733,19 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_composite(struct clk_hw *hw);
|
||||
|
||||
/***
|
||||
* struct clk_gpio_gate - gpio gated clock
|
||||
/**
|
||||
* struct clk_gpio - gpio gated clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @gpiod: gpio descriptor
|
||||
*
|
||||
* Clock with a gpio control for enabling and disabling the parent clock.
|
||||
* Implements .enable, .disable and .is_enabled
|
||||
* Clock with a gpio control for enabling and disabling the parent clock
|
||||
* or switching between two parents by asserting or deasserting the gpio.
|
||||
*
|
||||
* Implements .enable, .disable and .is_enabled or
|
||||
* .get_parent, .set_parent and .determine_rate depending on which clk_ops
|
||||
* is used.
|
||||
*/
|
||||
|
||||
struct clk_gpio {
|
||||
struct clk_hw hw;
|
||||
struct gpio_desc *gpiod;
|
||||
|
|
@ -738,16 +762,6 @@ struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
|
||||
|
||||
/**
|
||||
* struct clk_gpio_mux - gpio controlled clock multiplexer
|
||||
*
|
||||
* @hw: see struct clk_gpio
|
||||
* @gpiod: gpio descriptor to select the parent of this clock multiplexer
|
||||
*
|
||||
* Clock with a gpio control for selecting the parent clock.
|
||||
* Implements .get_parent, .set_parent and .determine_rate
|
||||
*/
|
||||
|
||||
extern const struct clk_ops clk_gpio_mux_ops;
|
||||
struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
|
||||
|
|
@ -757,17 +771,6 @@ struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
|
||||
|
||||
/**
|
||||
* clk_register - allocate a new clock, register it and return an opaque cookie
|
||||
* @dev: device that is registering this clock
|
||||
* @hw: link to hardware-specific clock data
|
||||
*
|
||||
* clk_register is the primary interface for populating the clock tree with new
|
||||
* clock nodes. It returns a pointer to the newly allocated struct clk which
|
||||
* cannot be dereferenced by driver code but may be used in conjuction with the
|
||||
* rest of the clock API. In the event of an error clk_register will return an
|
||||
* error code; drivers must test for an error code after calling clk_register.
|
||||
*/
|
||||
struct clk *clk_register(struct device *dev, struct clk_hw *hw);
|
||||
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
|
||||
|
||||
|
|
@ -993,37 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
|
|||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
/*
|
||||
* wrap access to peripherals in accessor routines
|
||||
* for improved portability across platforms
|
||||
*/
|
||||
|
||||
#if IS_ENABLED(CONFIG_PPC)
|
||||
|
||||
static inline u32 clk_readl(u32 __iomem *reg)
|
||||
{
|
||||
return ioread32be(reg);
|
||||
}
|
||||
|
||||
static inline void clk_writel(u32 val, u32 __iomem *reg)
|
||||
{
|
||||
iowrite32be(val, reg);
|
||||
}
|
||||
|
||||
#else /* platform dependent I/O accessors */
|
||||
|
||||
static inline u32 clk_readl(u32 __iomem *reg)
|
||||
{
|
||||
return readl(reg);
|
||||
}
|
||||
|
||||
static inline void clk_writel(u32 val, u32 __iomem *reg)
|
||||
{
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
#endif /* platform dependent I/O accessors */
|
||||
|
||||
void clk_gate_restore_context(struct clk_hw *hw);
|
||||
|
||||
#endif /* CONFIG_COMMON_CLK */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue