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MIPS: Cavium: Add EDAC support.

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Drivers for EDAC on Cavium.  Supported subsystems are:

 o CPU primary caches.  These are parity protected only, so only error
   reporting.
 o Second level cache - ECC protected, provides SECDED.
 o Memory: ECC / SECDEC if used with suitable DRAM modules.  The driver will
   will only initialize if ECC is enabled on a system so is safe to run on
   non-ECC memory.
 o PCI: Parity error reporting

Since it is very hard to test this sort of code the implementation is very
conservative and uses polling where possible for now.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Ralf Baechle 2012-10-17 00:39:09 +02:00
parent aa1762f49c
commit f65aad4177
12 changed files with 724 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/mips/pci/pci-octeon.c
View file

@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/swiotlb.h>
#include <asm/time.h>
@ -704,6 +705,9 @@ static int __init octeon_pci_setup(void)
*/
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
if (IS_ERR(platform_device_register_simple("co_pci_edac", 0, NULL, 0)))
pr_err("Registation of co_pci_edac failed!\n");
octeon_pci_dma_init();
return 0;