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ath9k_hw: fix more bitfield related endian issues

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A few LNA control related flags were also specified as a bitfields, however
for some strange reason they were written in big-endian order this time.
Fix this by using flags instead.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Felix Fietkau 2010-12-01 19:07:47 +01:00 • committed by John W. Linville
parent e702ba18f2
commit f67e07eb3d
2 changed files with 16 additions and 9 deletions
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14
drivers/net/wireless/ath/ath9k/eeprom.h
View file

@ -236,6 +236,15 @@
#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
#define LNA_CTL_BUF_MODE BIT(0)
#define LNA_CTL_ISEL_LO BIT(1)
#define LNA_CTL_ISEL_HI BIT(2)
#define LNA_CTL_BUF_IN BIT(3)
#define LNA_CTL_FEM_BAND BIT(4)
#define LNA_CTL_LOCAL_BIAS BIT(5)
#define LNA_CTL_FORCE_XPA BIT(6)
#define LNA_CTL_USE_ANT1 BIT(7)
enum eeprom_param { enum eeprom_param {
EEP_NFTHRESH_5, EEP_NFTHRESH_5,
EEP_NFTHRESH_2, EEP_NFTHRESH_2,
@ -381,10 +390,7 @@ struct modal_eep_header {
u8 xatten2Margin[AR5416_MAX_CHAINS]; u8 xatten2Margin[AR5416_MAX_CHAINS];
u8 ob_ch1; u8 ob_ch1;
u8 db_ch1; u8 db_ch1;
u8 useAnt1:1, u8 lna_ctl;
force_xpaon:1,
local_bias:1,
femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
u8 miscBits; u8 miscBits;
u16 xpaBiasLvlFreq[3]; u16 xpaBiasLvlFreq[3];
u8 futureModal[6]; u8 futureModal[6];

9
drivers/net/wireless/ath/ath9k/eeprom_def.c
View file

@ -451,9 +451,10 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
AR_AN_TOP2_LOCALBIAS, AR_AN_TOP2_LOCALBIAS,
AR_AN_TOP2_LOCALBIAS_S, AR_AN_TOP2_LOCALBIAS_S,
pModal->local_bias); !!(pModal->lna_ctl &
LNA_CTL_LOCAL_BIAS));
REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
pModal->force_xpaon); !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
} }
REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
@ -1428,8 +1429,8 @@ static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
num_ant_config = 1; num_ant_config = 1;
if (pBase->version >= 0x0E0D) if (pBase->version >= 0x0E0D &&
if (pModal->useAnt1) (pModal->lna_ctl & LNA_CTL_USE_ANT1))
num_ant_config += 1; num_ant_config += 1;
return num_ant_config; return num_ant_config;