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PCI: Fix whitespace, capitalization, and spelling errors

Browse source 
Fix whitespace, capitalization, and spelling errors.  No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.

Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Bjorn Helgaas 2013-11-14 11:28:18 -07:00
parent 4fbf888acc
commit f7625980f5
65 changed files with 518 additions and 520 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/pci/ats.c
View file

@ -410,7 +410,7 @@ EXPORT_SYMBOL_GPL(pci_disable_pasid);
* Otherwise is returns a bitmask with supported features. Current * Otherwise is returns a bitmask with supported features. Current
* features reported are: * features reported are:
* PCI_PASID_CAP_EXEC - Execute permission supported * PCI_PASID_CAP_EXEC - Execute permission supported
* PCI_PASID_CAP_PRIV - Priviledged mode supported * PCI_PASID_CAP_PRIV - Privileged mode supported
*/ */
int pci_pasid_features(struct pci_dev *pdev) int pci_pasid_features(struct pci_dev *pdev)
{ {

12
drivers/pci/host/pci-tegra.c
View file

@ -249,7 +249,7 @@ struct tegra_pcie {
void __iomem *afi; void __iomem *afi;
int irq; int irq;
struct list_head busses; struct list_head buses;
struct resource *cs; struct resource *cs;
struct resource io; struct resource io;
@ -399,14 +399,14 @@ free:
/* /*
* Look up a virtual address mapping for the specified bus number. If no such * Look up a virtual address mapping for the specified bus number. If no such
* mapping existis, try to create one. * mapping exists, try to create one.
*/ */
static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie, static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
unsigned int busnr) unsigned int busnr)
{ {
struct tegra_pcie_bus *bus; struct tegra_pcie_bus *bus;
list_for_each_entry(bus, &pcie->busses, list) list_for_each_entry(bus, &pcie->buses, list)
if (bus->nr == busnr) if (bus->nr == busnr)
return (void __iomem *)bus->area->addr; return (void __iomem *)bus->area->addr;
@ -414,7 +414,7 @@ static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
if (IS_ERR(bus)) if (IS_ERR(bus))
return NULL; return NULL;
list_add_tail(&bus->list, &pcie->busses); list_add_tail(&bus->list, &pcie->buses);
return (void __iomem *)bus->area->addr; return (void __iomem *)bus->area->addr;
} }
@ -808,7 +808,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
afi_writel(pcie, value, AFI_FUSE); afi_writel(pcie, value, AFI_FUSE);
/* initialze internal PHY, enable up to 16 PCIE lanes */ /* initialize internal PHY, enable up to 16 PCIE lanes */
pads_writel(pcie, 0x0, PADS_CTL_SEL); pads_writel(pcie, 0x0, PADS_CTL_SEL);
/* override IDDQ to 1 on all 4 lanes */ /* override IDDQ to 1 on all 4 lanes */
@ -1624,7 +1624,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
if (!pcie) if (!pcie)
return -ENOMEM; return -ENOMEM;
INIT_LIST_HEAD(&pcie->busses); INIT_LIST_HEAD(&pcie->buses);
INIT_LIST_HEAD(&pcie->ports); INIT_LIST_HEAD(&pcie->ports);
pcie->soc_data = match->data; pcie->soc_data = match->data;
pcie->dev = &pdev->dev; pcie->dev = &pdev->dev;

2
drivers/pci/host/pcie-designware.c
View file

@ -197,7 +197,7 @@ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
return -ENOSPC; return -ENOSPC;
/* /*
* Check if this position is at correct offset.nvec is always a * Check if this position is at correct offset.nvec is always a
* power of two. pos0 must be nvec bit alligned. * power of two. pos0 must be nvec bit aligned.
*/ */
if (pos % msgvec) if (pos % msgvec)
pos += msgvec - (pos % msgvec); pos += msgvec - (pos % msgvec);

6
drivers/pci/hotplug/acpiphp_core.c
View file

@ -169,8 +169,8 @@ static int disable_slot(struct hotplug_slot *hotplug_slot)
* was registered with us. This allows hardware specific * was registered with us. This allows hardware specific
* ACPI implementations to blink the light for us. * ACPI implementations to blink the light for us.
*/ */
static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status) static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status)
{ {
int retval = -ENODEV; int retval = -ENODEV;
pr_debug("%s - physical_slot = %s\n", __func__, pr_debug("%s - physical_slot = %s\n", __func__,
@ -182,7 +182,7 @@ static int disable_slot(struct hotplug_slot *hotplug_slot)
} else } else
attention_info = NULL; attention_info = NULL;
return retval; return retval;
} }
/** /**

2
drivers/pci/hotplug/acpiphp_glue.c
View file

@ -325,7 +325,7 @@ static acpi_status register_slot(acpi_handle handle, u32 lvl, void *data,
list_add_tail(&slot->node, &bridge->slots); list_add_tail(&slot->node, &bridge->slots);
/* Register slots for ejectable funtions only. */ /* Register slots for ejectable functions only. */
if (acpi_pci_check_ejectable(pbus, handle) || is_dock_device(handle)) { if (acpi_pci_check_ejectable(pbus, handle) || is_dock_device(handle)) {
unsigned long long sun; unsigned long long sun;
int retval; int retval;

2
drivers/pci/hotplug/acpiphp_ibm.c
View file

@ -259,7 +259,7 @@ static void ibm_handle_events(acpi_handle handle, u32 event, void *context)
pr_debug("%s: Received notification %02x\n", __func__, event); pr_debug("%s: Received notification %02x\n", __func__, event);
if (subevent == 0x80) { if (subevent == 0x80) {
pr_debug("%s: generationg bus event\n", __func__); pr_debug("%s: generating bus event\n", __func__);
acpi_bus_generate_netlink_event(note->device->pnp.device_class, acpi_bus_generate_netlink_event(note->device->pnp.device_class,
dev_name(&note->device->dev), dev_name(&note->device->dev),
note->event, detail); note->event, detail);

2
drivers/pci/hotplug/cpcihp_generic.c
View file

@ -53,7 +53,7 @@
#define dbg(format, arg...) \ #define dbg(format, arg...) \
do { \ do { \
if(debug) \ if (debug) \
printk (KERN_DEBUG "%s: " format "\n", \ printk (KERN_DEBUG "%s: " format "\n", \
MY_NAME , ## arg); \ MY_NAME , ## arg); \
} while(0) } while(0)

2
drivers/pci/hotplug/cpcihp_zt5550.c
View file

@ -48,7 +48,7 @@
#define dbg(format, arg...) \ #define dbg(format, arg...) \
do { \ do { \
if(debug) \ if (debug) \
printk (KERN_DEBUG "%s: " format "\n", \ printk (KERN_DEBUG "%s: " format "\n", \
MY_NAME , ## arg); \ MY_NAME , ## arg); \
} while(0) } while(0)

4
drivers/pci/hotplug/cpqphp_core.c
View file

@ -862,10 +862,10 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_disable_device; goto err_disable_device;
} }
/* Check for the proper subsystem ID's /* Check for the proper subsystem IDs
* Intel uses a different SSID programming model than Compaq. * Intel uses a different SSID programming model than Compaq.
* For Intel, each SSID bit identifies a PHP capability. * For Intel, each SSID bit identifies a PHP capability.
* Also Intel HPC's may have RID=0. * Also Intel HPCs may have RID=0.
*/ */
if ((pdev->revision <= 2) && (vendor_id != PCI_VENDOR_ID_INTEL)) { if ((pdev->revision <= 2) && (vendor_id != PCI_VENDOR_ID_INTEL)) {
err(msg_HPC_not_supported); err(msg_HPC_not_supported);

6
drivers/pci/hotplug/cpqphp_ctrl.c
View file

@ -2411,11 +2411,11 @@ static int configure_new_function(struct controller *ctrl, struct pci_func *func
if (rc) if (rc)
return rc; return rc;
/* find range of busses to use */ /* find range of buses to use */
dbg("find ranges of buses to use\n"); dbg("find ranges of buses to use\n");
bus_node = get_max_resource(&(resources->bus_head), 1); bus_node = get_max_resource(&(resources->bus_head), 1);
/* If we don't have any busses to allocate, we can't continue */ /* If we don't have any buses to allocate, we can't continue */
if (!bus_node) if (!bus_node)
return -ENOMEM; return -ENOMEM;
@ -2900,7 +2900,7 @@ static int configure_new_function(struct controller *ctrl, struct pci_func *func
/* If this function needs an interrupt and we are behind /* If this function needs an interrupt and we are behind
* a bridge and the pin is tied to something that's * a bridge and the pin is tied to something that's
* alread mapped, set this one the same */ * already mapped, set this one the same */
if (temp_byte && resources->irqs && if (temp_byte && resources->irqs &&
(resources->irqs->valid_INT & (resources->irqs->valid_INT &
(0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) { (0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) {

5
drivers/pci/hotplug/cpqphp_pci.c
View file

@ -291,7 +291,7 @@ int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 s
* *
* Reads configuration for all slots in a PCI bus and saves info. * Reads configuration for all slots in a PCI bus and saves info.
* *
* Note: For non-hot plug busses, the slot # saved is the device # * Note: For non-hot plug buses, the slot # saved is the device #
* *
* returns 0 if success * returns 0 if success
*/ */
@ -455,7 +455,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
* cpqhp_save_slot_config * cpqhp_save_slot_config
* *
* Saves configuration info for all PCI devices in a given slot * Saves configuration info for all PCI devices in a given slot
* including subordinate busses. * including subordinate buses.
* *
* returns 0 if success * returns 0 if success
*/ */
@ -1556,4 +1556,3 @@ void cpqhp_destroy_board_resources (struct pci_func * func)
kfree(tres); kfree(tres);
} }
} }

4
drivers/pci/hotplug/ibmphp.h
View file

@ -59,7 +59,7 @@ extern int ibmphp_debug;
/************************************************************ /************************************************************
* RESOURE TYPE * * RESOURCE TYPE *
************************************************************/ ************************************************************/
#define EBDA_RSRC_TYPE_MASK 0x03 #define EBDA_RSRC_TYPE_MASK 0x03
@ -574,7 +574,7 @@ void ibmphp_hpc_stop_poll_thread(void);
#define HPC_CTLR_IRQ_PENDG 0x80 #define HPC_CTLR_IRQ_PENDG 0x80
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// HPC_CTLR_WROKING status return codes // HPC_CTLR_WORKING status return codes
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
#define HPC_CTLR_WORKING_NO 0x00 #define HPC_CTLR_WORKING_NO 0x00
#define HPC_CTLR_WORKING_YES 0x01 #define HPC_CTLR_WORKING_YES 0x01

17
drivers/pci/hotplug/ibmphp_core.c
View file

@ -58,7 +58,7 @@ MODULE_DESCRIPTION (DRIVER_DESC);
struct pci_bus *ibmphp_pci_bus; struct pci_bus *ibmphp_pci_bus;
static int max_slots; static int max_slots;
static int irqs[16]; /* PIC mode IRQ's we're using so far (in case MPS static int irqs[16]; /* PIC mode IRQs we're using so far (in case MPS
* tables don't provide default info for empty slots */ * tables don't provide default info for empty slots */
static int init_flag; static int init_flag;
@ -172,7 +172,7 @@ int ibmphp_init_devno(struct slot **cur_slot)
debug("(*cur_slot)->irq[3] = %x\n", debug("(*cur_slot)->irq[3] = %x\n",
(*cur_slot)->irq[3]); (*cur_slot)->irq[3]);
debug("rtable->exlusive_irqs = %x\n", debug("rtable->exclusive_irqs = %x\n",
rtable->exclusive_irqs); rtable->exclusive_irqs);
debug("rtable->slots[loop].irq[0].bitmap = %x\n", debug("rtable->slots[loop].irq[0].bitmap = %x\n",
rtable->slots[loop].irq[0].bitmap); rtable->slots[loop].irq[0].bitmap);
@ -1210,7 +1210,7 @@ int ibmphp_do_disable_slot(struct slot *slot_cur)
attn_LED_blink(slot_cur); attn_LED_blink(slot_cur);
if (slot_cur->func == NULL) { if (slot_cur->func == NULL) {
/* We need this for fncs's that were there on bootup */ /* We need this for functions that were there on bootup */
slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL); slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL);
if (!slot_cur->func) { if (!slot_cur->func) {
err("out of system memory\n"); err("out of system memory\n");
@ -1223,11 +1223,12 @@ int ibmphp_do_disable_slot(struct slot *slot_cur)
ibm_unconfigure_device(slot_cur->func); ibm_unconfigure_device(slot_cur->func);
/* If we got here from latch suddenly opening on operating card or /*
a power fault, there's no power to the card, so cannot * If we got here from latch suddenly opening on operating card or
read from it to determine what resources it occupied. This operation * a power fault, there's no power to the card, so cannot
is forbidden anyhow. The best we can do is remove it from kernel * read from it to determine what resources it occupied. This operation
lists at least */ * is forbidden anyhow. The best we can do is remove it from kernel
* lists at least */
if (!flag) { if (!flag) {
attn_off(slot_cur); attn_off(slot_cur);

5
drivers/pci/hotplug/ibmphp_ebda.c
View file

@ -330,7 +330,7 @@ int __init ibmphp_access_ebda (void)
debug ("info about hpc descriptor---\n"); debug ("info about hpc descriptor---\n");
debug ("hot blk format: %x\n", format); debug ("hot blk format: %x\n", format);
debug ("num of controller: %x\n", num_ctlrs); debug ("num of controller: %x\n", num_ctlrs);
debug ("offset of hpc data structure enteries: %x\n ", sub_addr); debug ("offset of hpc data structure entries: %x\n ", sub_addr);
sub_addr = base + re; /* re sub blk */ sub_addr = base + re; /* re sub blk */
/* FIXME: rc is never used/checked */ /* FIXME: rc is never used/checked */
@ -359,7 +359,7 @@ int __init ibmphp_access_ebda (void)
debug ("info about rsrc descriptor---\n"); debug ("info about rsrc descriptor---\n");
debug ("format: %x\n", format); debug ("format: %x\n", format);
debug ("num of rsrc: %x\n", num_entries); debug ("num of rsrc: %x\n", num_entries);
debug ("offset of rsrc data structure enteries: %x\n ", sub_addr); debug ("offset of rsrc data structure entries: %x\n ", sub_addr);
hs_complete = 1; hs_complete = 1;
} else { } else {
@ -1210,4 +1210,3 @@ static int ibmphp_probe (struct pci_dev * dev, const struct pci_device_id *ids)
} }
return -ENODEV; return -ENODEV;
} }

5
drivers/pci/hotplug/ibmphp_pci.c
View file

@ -371,7 +371,7 @@ static int configure_device (struct pci_func *func)
for (count = 0; address[count]; count++) { /* for 6 BARs */ for (count = 0; address[count]; count++) { /* for 6 BARs */
/* not sure if i need this. per scott, said maybe need smth like this /* not sure if i need this. per scott, said maybe need * something like this
if devices don't adhere 100% to the spec, so don't want to write if devices don't adhere 100% to the spec, so don't want to write
to the reserved bits to the reserved bits
@ -1071,7 +1071,7 @@ error:
* This function adds up the amount of resources needed behind the PPB bridge * This function adds up the amount of resources needed behind the PPB bridge
* and passes it to the configure_bridge function * and passes it to the configure_bridge function
* Input: bridge function * Input: bridge function
* Ouput: amount of resources needed * Output: amount of resources needed
*****************************************************************************/ *****************************************************************************/
static struct res_needed *scan_behind_bridge (struct pci_func * func, u8 busno) static struct res_needed *scan_behind_bridge (struct pci_func * func, u8 busno)
{ {
@ -1726,4 +1726,3 @@ static u8 find_sec_number (u8 primary_busno, u8 slotno)
return busno; return busno;
return 0xff; return 0xff;
} }

12
drivers/pci/hotplug/ibmphp_res.c
View file

@ -609,7 +609,7 @@ int ibmphp_add_resource (struct resource_node *res)
bus_cur = find_bus_wprev (res->busno, NULL, 0); bus_cur = find_bus_wprev (res->busno, NULL, 0);
if (!bus_cur) { if (!bus_cur) {
/* didn't find a bus, smth's wrong!!! */ /* didn't find a bus, something's wrong!!! */
debug ("no bus in the system, either pci_dev's wrong or allocation failed\n"); debug ("no bus in the system, either pci_dev's wrong or allocation failed\n");
return -ENODEV; return -ENODEV;
} }
@ -770,7 +770,7 @@ int ibmphp_add_resource (struct resource_node *res)
* This routine will remove the resource from the list of resources * This routine will remove the resource from the list of resources
* *
* Input: io, mem, and/or pfmem resource to be deleted * Input: io, mem, and/or pfmem resource to be deleted
* Ouput: modified resource list * Output: modified resource list
* 0 or error code * 0 or error code
****************************************************************************/ ****************************************************************************/
int ibmphp_remove_resource (struct resource_node *res) int ibmphp_remove_resource (struct resource_node *res)
@ -966,7 +966,7 @@ static struct range_node * find_range (struct bus_node *bus_cur, struct resource
* otherwise, returns 0 * otherwise, returns 0
* *
* Input: resource * Input: resource
* Ouput: the correct start and end address are inputted into the resource node, * Output: the correct start and end address are inputted into the resource node,
* 0 or -EINVAL * 0 or -EINVAL
*****************************************************************************/ *****************************************************************************/
int ibmphp_check_resource (struct resource_node *res, u8 bridge) int ibmphp_check_resource (struct resource_node *res, u8 bridge)
@ -996,7 +996,7 @@ int ibmphp_check_resource (struct resource_node *res, u8 bridge)
bus_cur = find_bus_wprev (res->busno, NULL, 0); bus_cur = find_bus_wprev (res->busno, NULL, 0);
if (!bus_cur) { if (!bus_cur) {
/* didn't find a bus, smth's wrong!!! */ /* didn't find a bus, something's wrong!!! */
debug ("no bus in the system, either pci_dev's wrong or allocation failed\n"); debug ("no bus in the system, either pci_dev's wrong or allocation failed\n");
return -EINVAL; return -EINVAL;
} }
@ -1344,7 +1344,7 @@ int ibmphp_check_resource (struct resource_node *res, u8 bridge)
* This routine is called from remove_card if the card contained PPB. * This routine is called from remove_card if the card contained PPB.
* It will remove all the resources on the bus as well as the bus itself * It will remove all the resources on the bus as well as the bus itself
* Input: Bus * Input: Bus
* Ouput: 0, -ENODEV * Output: 0, -ENODEV
********************************************************************************/ ********************************************************************************/
int ibmphp_remove_bus (struct bus_node *bus, u8 parent_busno) int ibmphp_remove_bus (struct bus_node *bus, u8 parent_busno)
{ {
@ -1920,7 +1920,7 @@ static int range_exists_already (struct range_node * range, struct bus_node * bu
* Returns: none * Returns: none
* Note: this function doesn't take into account IO restrictions etc, * Note: this function doesn't take into account IO restrictions etc,
* so will only work for bridges with no video/ISA devices behind them It * so will only work for bridges with no video/ISA devices behind them It
* also will not work for onboard PPB's that can have more than 1 *bus * also will not work for onboard PPBs that can have more than 1 *bus
* behind them All these are TO DO. * behind them All these are TO DO.
* Also need to add more error checkings... (from fnc returns etc) * Also need to add more error checkings... (from fnc returns etc)
*/ */

2
drivers/pci/hotplug/pciehp_acpi.c
View file

@ -78,7 +78,7 @@ static int __initdata dup_slot_id;
static int __initdata acpi_slot_detected; static int __initdata acpi_slot_detected;
static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots); static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots);
/* Dummy driver for dumplicate name detection */ /* Dummy driver for duplicate name detection */
static int __init dummy_probe(struct pcie_device *dev) static int __init dummy_probe(struct pcie_device *dev)
{ {
u32 slot_cap; u32 slot_cap;

4
drivers/pci/hotplug/pciehp_hpc.c
View file

@ -194,7 +194,7 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
} else if (!NO_CMD_CMPL(ctrl)) { } else if (!NO_CMD_CMPL(ctrl)) {
/* /*
* This controller semms to notify of command completed * This controller seems to notify of command completed
* event even though it supports none of power * event even though it supports none of power
* controller, attention led, power led and EMI. * controller, attention led, power led and EMI.
*/ */
@ -926,7 +926,7 @@ struct controller *pcie_init(struct pcie_device *dev)
if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
goto abort_ctrl; goto abort_ctrl;
/* Disable sotfware notification */ /* Disable software notification */
pcie_disable_notification(ctrl); pcie_disable_notification(ctrl);
ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",

2
drivers/pci/hotplug/rpadlpar_core.c
View file

@ -217,7 +217,7 @@ static int dlpar_remove_phb(char *drc_name, struct device_node *dn)
if (!pcibios_find_pci_bus(dn)) if (!pcibios_find_pci_bus(dn))
return -EINVAL; return -EINVAL;
/* If pci slot is hotplugable, use hotplug to remove it */ /* If pci slot is hotpluggable, use hotplug to remove it */
slot = find_php_slot(dn); slot = find_php_slot(dn);
if (slot && rpaphp_deregister_slot(slot)) { if (slot && rpaphp_deregister_slot(slot)) {
printk(KERN_ERR "%s: unable to remove hotplug slot %s\n", printk(KERN_ERR "%s: unable to remove hotplug slot %s\n",

2
drivers/pci/hotplug/rpaphp_core.c
View file

@ -289,7 +289,7 @@ static int is_php_dn(struct device_node *dn, const int **indexes,
* rpaphp_add_slot -- declare a hotplug slot to the hotplug subsystem. * rpaphp_add_slot -- declare a hotplug slot to the hotplug subsystem.
* @dn: device node of slot * @dn: device node of slot
* *
* This subroutine will register a hotplugable slot with the * This subroutine will register a hotpluggable slot with the
* PCI hotplug infrastructure. This routine is typically called * PCI hotplug infrastructure. This routine is typically called
* during boot time, if the hotplug slots are present at boot time, * during boot time, if the hotplug slots are present at boot time,
* or is called later, by the dlpar add code, if the slot is * or is called later, by the dlpar add code, if the slot is

1
drivers/pci/hotplug/rpaphp_pci.c
View file

@ -133,4 +133,3 @@ int rpaphp_enable_slot(struct slot *slot)
return 0; return 0;
} }

1
drivers/pci/hotplug/rpaphp_slot.c
View file

@ -145,4 +145,3 @@ int rpaphp_register_slot(struct slot *slot)
info("Slot [%s] registered\n", slot->name); info("Slot [%s] registered\n", slot->name);
return 0; return 0;
} }

2
drivers/pci/hotplug/shpchp_hpc.c
View file

@ -116,7 +116,7 @@
#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
/* /*
* SHPC Command Code definitnions * SHPC Command Code definitions
* *
* Slot Operation 00h - 3Fh * Slot Operation 00h - 3Fh
* Set Bus Segment Speed/Mode A 40h - 47h * Set Bus Segment Speed/Mode A 40h - 47h

2
drivers/pci/msi.c
View file

@ -784,7 +784,7 @@ error:
* @nvec: how many MSIs have been requested ? * @nvec: how many MSIs have been requested ?
* @type: are we checking for MSI or MSI-X ? * @type: are we checking for MSI or MSI-X ?
* *
* Look at global flags, the device itself, and its parent busses * Look at global flags, the device itself, and its parent buses
* to determine if MSI/-X are supported for the device. If MSI/-X is * to determine if MSI/-X are supported for the device. If MSI/-X is
* supported return 0, else return an error code. * supported return 0, else return an error code.
**/ **/

12
drivers/pci/pci-sysfs.c
View file

@ -270,13 +270,17 @@ msi_bus_store(struct device *dev, struct device_attribute *attr,
if (kstrtoul(buf, 0, &val) < 0) if (kstrtoul(buf, 0, &val) < 0)
return -EINVAL; return -EINVAL;
/* bad things may happen if the no_msi flag is changed /*
* while some drivers are loaded */ * Bad things may happen if the no_msi flag is changed
* while drivers are loaded.
*/
if (!capable(CAP_SYS_ADMIN)) if (!capable(CAP_SYS_ADMIN))
return -EPERM; return -EPERM;
/* Maybe pci devices without subordinate busses shouldn't even have this /*
* attribute in the first place? */ * Maybe devices without subordinate buses shouldn't have this
* attribute in the first place?
*/
if (!pdev->subordinate) if (!pdev->subordinate)
return count; return count;

14
drivers/pci/pci.c
View file

@ -1030,7 +1030,7 @@ struct pci_saved_state {
* the device saved state. * the device saved state.
* @dev: PCI device that we're dealing with * @dev: PCI device that we're dealing with
* *
* Rerturn NULL if no state or error. * Return NULL if no state or error.
*/ */
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
{ {
@ -1880,7 +1880,7 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
* pci_dev_run_wake - Check if device can generate run-time wake-up events. * pci_dev_run_wake - Check if device can generate run-time wake-up events.
* @dev: Device to check. * @dev: Device to check.
* *
* Return true if the device itself is cabable of generating wake-up events * Return true if the device itself is capable of generating wake-up events
* (through the platform or using the native PCIe PME) or if the device supports * (through the platform or using the native PCIe PME) or if the device supports
* PME and one of its upstream bridges can generate wake-up events. * PME and one of its upstream bridges can generate wake-up events.
*/ */
@ -2447,7 +2447,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
switch (pci_pcie_type(pdev)) { switch (pci_pcie_type(pdev)) {
/* /*
* PCI/X-to-PCIe bridges are not specifically mentioned by the spec, * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
* but since their primary inteface is PCI/X, we conservatively * but since their primary interface is PCI/X, we conservatively
* handle them as we would a non-PCIe device. * handle them as we would a non-PCIe device.
*/ */
case PCI_EXP_TYPE_PCIE_BRIDGE: case PCI_EXP_TYPE_PCIE_BRIDGE:
@ -2471,7 +2471,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
/* /*
* PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
* implemented by the remaining PCIe types to indicate peer-to-peer * implemented by the remaining PCIe types to indicate peer-to-peer
* capabilities, but only when they are part of a multifunciton * capabilities, but only when they are part of a multifunction
* device. The footnote for section 6.12 indicates the specific * device. The footnote for section 6.12 indicates the specific
* PCIe types included here. * PCIe types included here.
*/ */
@ -2486,7 +2486,7 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
} }
/* /*
* PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
* to single function devices with the exception of downstream ports. * to single function devices with the exception of downstream ports.
*/ */
return true; return true;
@ -3292,7 +3292,7 @@ clear:
* *
* NOTE: This causes the caller to sleep for twice the device power transition * NOTE: This causes the caller to sleep for twice the device power transition
* cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
* by devault (i.e. unless the @dev's d3_delay field has a different value). * by default (i.e. unless the @dev's d3_delay field has a different value).
* Moreover, only devices in D0 can be reset by this function. * Moreover, only devices in D0 can be reset by this function.
*/ */
static int pci_pm_reset(struct pci_dev *dev, int probe) static int pci_pm_reset(struct pci_dev *dev, int probe)
@ -3341,7 +3341,7 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
/* /*
* PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
* this to 2ms to ensure that we meet the minium requirement. * this to 2ms to ensure that we meet the minimum requirement.
*/ */
msleep(2); msleep(2);

2
drivers/pci/pcie/aer/aerdrv_core.c
View file

@ -525,7 +525,7 @@ static void handle_error_source(struct pcie_device *aerdev,
if (info->severity == AER_CORRECTABLE) { if (info->severity == AER_CORRECTABLE) {
/* /*
* Correctable error does not need software intevention. * Correctable error does not need software intervention.
* No need to go through error recovery process. * No need to go through error recovery process.
*/ */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

2
drivers/pci/pcie/aspm.c
View file

@ -548,7 +548,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
/* /*
* pcie_aspm_init_link_state: Initiate PCI express link state. * pcie_aspm_init_link_state: Initiate PCI express link state.
* It is called after the pcie and its children devices are scaned. * It is called after the pcie and its children devices are scanned.
* @pdev: the root port or switch downstream port * @pdev: the root port or switch downstream port
*/ */
void pcie_aspm_init_link_state(struct pci_dev *pdev) void pcie_aspm_init_link_state(struct pci_dev *pdev)

2
drivers/pci/pcie/portdrv.h
View file

@ -14,7 +14,7 @@
#define PCIE_PORT_DEVICE_MAXSERVICES 4 #define PCIE_PORT_DEVICE_MAXSERVICES 4
/* /*
* According to the PCI Express Base Specification 2.0, the indices of * According to the PCI Express Base Specification 2.0, the indices of
* the MSI-X table entires used by port services must not exceed 31 * the MSI-X table entries used by port services must not exceed 31
*/ */
#define PCIE_PORT_MAX_MSIX_ENTRIES 32 #define PCIE_PORT_MAX_MSIX_ENTRIES 32

2
drivers/pci/pcie/portdrv_core.c
View file

@ -46,7 +46,7 @@ static void release_pcie_device(struct device *dev)
* pcie_port_msix_add_entry - add entry to given array of MSI-X entries * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
* @entries: Array of MSI-X entries * @entries: Array of MSI-X entries
* @new_entry: Index of the entry to add to the array * @new_entry: Index of the entry to add to the array
* @nr_entries: Number of entries aleady in the array * @nr_entries: Number of entries already in the array
* *
* Return value: Position of the added entry in the array * Return value: Position of the added entry in the array
*/ */

2
drivers/pci/proc.c
View file

@ -222,7 +222,7 @@ static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
default: default:
ret = -EINVAL; ret = -EINVAL;
break; break;
}; }
return ret; return ret;
} }

24
drivers/pci/quirks.c
View file

@ -55,7 +55,7 @@ static void quirk_mellanox_tavor(struct pci_dev *dev)
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
/* Deal with broken BIOS'es that neglect to enable passive release, /* Deal with broken BIOSes that neglect to enable passive release,
which can cause problems in combination with the 82441FX/PPro MTRRs */ which can cause problems in combination with the 82441FX/PPro MTRRs */
static void quirk_passive_release(struct pci_dev *dev) static void quirk_passive_release(struct pci_dev *dev)
{ {
@ -712,7 +712,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_i
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
/* /*
* VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
* This leads to doubled level interrupt rates. * This leads to doubled level interrupt rates.
* Set this bit to get rid of cycle wastage. * Set this bit to get rid of cycle wastage.
* Otherwise uncritical. * Otherwise uncritical.
@ -2127,8 +2127,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
#ifdef CONFIG_PCI_MSI #ifdef CONFIG_PCI_MSI
/* Some chipsets do not support MSI. We cannot easily rely on setting /* Some chipsets do not support MSI. We cannot easily rely on setting
* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
* some other busses controlled by the chipset even if Linux is not * some other buses controlled by the chipset even if Linux is not
* aware of it. Instead of setting the flag on all busses in the * aware of it. Instead of setting the flag on all buses in the
* machine, simply disable MSI globally. * machine, simply disable MSI globally.
*/ */
static void quirk_disable_all_msi(struct pci_dev *dev) static void quirk_disable_all_msi(struct pci_dev *dev)
@ -2288,14 +2288,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
nvenet_msi_disable); nvenet_msi_disable);
/* /*
* Some versions of the MCP55 bridge from nvidia have a legacy irq routing * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
* config register. This register controls the routing of legacy interrupts * config register. This register controls the routing of legacy
* from devices that route through the MCP55. If this register is misprogramed * interrupts from devices that route through the MCP55. If this register
* interrupts are only sent to the bsp, unlike conventional systems where the * is misprogrammed, interrupts are only sent to the BSP, unlike
* irq is broadxast to all online cpus. Not having this register set * conventional systems where the IRQ is broadcast to all online CPUs. Not
* properly prevents kdump from booting up properly, so lets make sure that * having this register set properly prevents kdump from booting up
* we have it set correctly. * properly, so let's make sure that we have it set correctly.
* Note this is an undocumented register. * Note that this is an undocumented register.
*/ */
static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
{ {

2
drivers/pci/search.c
View file

@ -96,7 +96,7 @@ struct pci_bus * pci_find_bus(int domain, int busnr)
* pci_find_next_bus - begin or continue searching for a PCI bus * pci_find_next_bus - begin or continue searching for a PCI bus
* @from: Previous PCI bus found, or %NULL for new search. * @from: Previous PCI bus found, or %NULL for new search.
* *
* Iterates through the list of known PCI busses. A new search is * Iterates through the list of known PCI buses. A new search is
* initiated by passing %NULL as the @from argument. Otherwise if * initiated by passing %NULL as the @from argument. Otherwise if
* @from is not %NULL, searches continue from next device on the * @from is not %NULL, searches continue from next device on the
* global list. * global list.

8
drivers/pci/setup-bus.c
View file

@ -292,8 +292,8 @@ static void assign_requested_resources_sorted(struct list_head *head,
(!(res->flags & IORESOURCE_ROM_ENABLE)))) (!(res->flags & IORESOURCE_ROM_ENABLE))))
add_to_list(fail_head, add_to_list(fail_head,
dev_res->dev, res, dev_res->dev, res,
0 /* dont care */, 0 /* don't care */,
0 /* dont care */); 0 /* don't care */);
} }
reset_resource(res); reset_resource(res);
} }
@ -950,7 +950,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
if (realloc_head && i >= PCI_IOV_RESOURCES && if (realloc_head && i >= PCI_IOV_RESOURCES &&
i <= PCI_IOV_RESOURCE_END) { i <= PCI_IOV_RESOURCE_END) {
r->end = r->start - 1; r->end = r->start - 1;
add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
children_add_size += r_size; children_add_size += r_size;
continue; continue;
} }
@ -1457,7 +1457,7 @@ static enum enable_type pci_realloc_detect(struct pci_bus *bus,
/* /*
* first try will not touch pci bridge res * first try will not touch pci bridge res
* second and later try will clear small leaf bridge res * second and later try will clear small leaf bridge res
* will stop till to the max deepth if can not find good one * will stop till to the max depth if can not find good one
*/ */
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
{ {

2
drivers/pci/syscall.c
View file

@ -44,7 +44,7 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn,
default: default:
err = -EINVAL; err = -EINVAL;
goto error; goto error;
}; }
err = -EIO; err = -EIO;
if (cfg_ret != PCIBIOS_SUCCESSFUL) if (cfg_ret != PCIBIOS_SUCCESSFUL)

47
include/linux/pci.h
View file

@ -32,7 +32,6 @@
#include <linux/irqreturn.h> #include <linux/irqreturn.h>
#include <uapi/linux/pci.h> #include <uapi/linux/pci.h>
/* Include the ID list */
#include <linux/pci_ids.h> #include <linux/pci_ids.h>
/* /*
@ -42,9 +41,10 @@
* *
* 7:3 = slot * 7:3 = slot
* 2:0 = function * 2:0 = function
* PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h *
* PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
* In the interest of not exposing interfaces to user-space unnecessarily, * In the interest of not exposing interfaces to user-space unnecessarily,
* the following kernel only defines are being added here. * the following kernel-only defines are being added here.
*/ */
#define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
@ -153,10 +153,10 @@ enum pcie_reset_state {
/* Reset is NOT asserted (Use to deassert reset) */ /* Reset is NOT asserted (Use to deassert reset) */
pcie_deassert_reset = (__force pcie_reset_state_t) 1, pcie_deassert_reset = (__force pcie_reset_state_t) 1,
/* Use #PERST to reset PCI-E device */ /* Use #PERST to reset PCIe device */
pcie_warm_reset = (__force pcie_reset_state_t) 2, pcie_warm_reset = (__force pcie_reset_state_t) 2,
/* Use PCI-E Hot Reset to reset device */ /* Use PCIe Hot Reset to reset device */
pcie_hot_reset = (__force pcie_reset_state_t) 3 pcie_hot_reset = (__force pcie_reset_state_t) 3
}; };
@ -259,13 +259,13 @@ struct pci_dev {
unsigned int class; /* 3 bytes: (base,sub,prog-if) */ unsigned int class; /* 3 bytes: (base,sub,prog-if) */
u8 revision; /* PCI revision, low byte of class word */ u8 revision; /* PCI revision, low byte of class word */
u8 hdr_type; /* PCI header type (`multi' flag masked out) */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */
u8 pcie_cap; /* PCI-E capability offset */ u8 pcie_cap; /* PCIe capability offset */
u8 msi_cap; /* MSI capability offset */ u8 msi_cap; /* MSI capability offset */
u8 msix_cap; /* MSI-X capability offset */ u8 msix_cap; /* MSI-X capability offset */
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
u8 rom_base_reg; /* which config register controls the ROM */ u8 rom_base_reg; /* which config register controls the ROM */
u8 pin; /* which interrupt pin this device uses */ u8 pin; /* which interrupt pin this device uses */
u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
struct pci_driver *driver; /* which driver has allocated this device */ struct pci_driver *driver; /* which driver has allocated this device */
u64 dma_mask; /* Mask of the bits of bus address this u64 dma_mask; /* Mask of the bits of bus address this
@ -300,7 +300,7 @@ struct pci_dev {
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
#ifdef CONFIG_PCIEASPM #ifdef CONFIG_PCIEASPM
struct pcie_link_state *link_state; /* ASPM link state. */ struct pcie_link_state *link_state; /* ASPM link state */
#endif #endif
pci_channel_state_t error_state; /* current connectivity state */ pci_channel_state_t error_state; /* current connectivity state */
@ -317,7 +317,7 @@ struct pci_dev {
bool match_driver; /* Skip attaching driver */ bool match_driver; /* Skip attaching driver */
/* These fields are used by common fixups */ /* These fields are used by common fixups */
unsigned int transparent:1; /* Transparent PCI bridge */ unsigned int transparent:1; /* Subtractive decode PCI bridge */
unsigned int multifunction:1;/* Part of multi-function device */ unsigned int multifunction:1;/* Part of multi-function device */
/* keep track of device state */ /* keep track of device state */
unsigned int is_added:1; unsigned int is_added:1;
@ -371,7 +371,6 @@ static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
if (dev->is_virtfn) if (dev->is_virtfn)
dev = dev->physfn; dev = dev->physfn;
#endif #endif
return dev; return dev;
} }
@ -456,7 +455,7 @@ struct pci_bus {
char name[48]; char name[48];
unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
pci_bus_flags_t bus_flags; /* Inherited by child busses */ pci_bus_flags_t bus_flags; /* inherited by child buses */
struct device *bridge; struct device *bridge;
struct device dev; struct device dev;
struct bin_attribute *legacy_io; /* legacy I/O for this bus */ struct bin_attribute *legacy_io; /* legacy I/O for this bus */
@ -468,7 +467,7 @@ struct pci_bus {
#define to_pci_bus(n) container_of(n, struct pci_bus, dev) #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
/* /*
* Returns true if the pci bus is root (behind host-pci bridge), * Returns true if the PCI bus is root (behind host-PCI bridge),
* false otherwise * false otherwise
* *
* Some code assumes that "bus->self == NULL" means that bus is a root bus. * Some code assumes that "bus->self == NULL" means that bus is a root bus.
@ -510,7 +509,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
#define PCIBIOS_BUFFER_TOO_SMALL 0x89 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
/* /*
* Translate above to generic errno for passing back through non-pci. * Translate above to generic errno for passing back through non-PCI code.
*/ */
static inline int pcibios_err_to_errno(int err) static inline int pcibios_err_to_errno(int err)
{ {
@ -561,9 +560,10 @@ struct pci_dynids {
struct list_head list; /* for IDs added at runtime */ struct list_head list; /* for IDs added at runtime */
}; };
/* ---------------------------------------------------------------- */
/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides /*
* a set of callbacks in struct pci_error_handlers, then that device driver * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
* a set of callbacks in struct pci_error_handlers, that device driver
* will be notified of PCI bus errors, and will be driven to recovery * will be notified of PCI bus errors, and will be driven to recovery
* when an error occurs. * when an error occurs.
*/ */
@ -609,7 +609,6 @@ struct pci_error_handlers {
void (*resume)(struct pci_dev *dev); void (*resume)(struct pci_dev *dev);
}; };
/* ---------------------------------------------------------------- */
struct module; struct module;
struct pci_driver { struct pci_driver {
@ -713,10 +712,10 @@ extern enum pcie_bus_config_types pcie_bus_config;
extern struct bus_type pci_bus_type; extern struct bus_type pci_bus_type;
/* Do NOT directly access these two variables, unless you are arch specific pci /* Do NOT directly access these two variables, unless you are arch-specific PCI
* code, or pci core code. */ * code, or PCI core code. */
extern struct list_head pci_root_buses; /* list of all known PCI buses */ extern struct list_head pci_root_buses; /* list of all known PCI buses */
/* Some device drivers need know if pci is initiated */ /* Some device drivers need know if PCI is initiated */
int no_pci_devices(void); int no_pci_devices(void);
void pcibios_resource_survey_bus(struct pci_bus *bus); void pcibios_resource_survey_bus(struct pci_bus *bus);
@ -724,7 +723,7 @@ void pcibios_add_bus(struct pci_bus *bus);
void pcibios_remove_bus(struct pci_bus *bus); void pcibios_remove_bus(struct pci_bus *bus);
void pcibios_fixup_bus(struct pci_bus *); void pcibios_fixup_bus(struct pci_bus *);
int __must_check pcibios_enable_device(struct pci_dev *, int mask); int __must_check pcibios_enable_device(struct pci_dev *, int mask);
/* Architecture specific versions may override this (weak) */ /* Architecture-specific versions may override this (weak) */
char *pcibios_setup(char *str); char *pcibios_setup(char *str);
/* Used only when drivers/pci/setup.c is used */ /* Used only when drivers/pci/setup.c is used */
@ -1258,7 +1257,7 @@ void pci_cfg_access_unlock(struct pci_dev *dev);
/* /*
* PCI domain support. Sometimes called PCI segment (eg by ACPI), * PCI domain support. Sometimes called PCI segment (eg by ACPI),
* a PCI domain is defined to be a set of PCI busses which share * a PCI domain is defined to be a set of PCI buses which share
* configuration space. * configuration space.
*/ */
#ifdef CONFIG_PCI_DOMAINS #ifdef CONFIG_PCI_DOMAINS
@ -1672,7 +1671,7 @@ extern u8 pci_cache_line_size;
extern unsigned long pci_hotplug_io_size; extern unsigned long pci_hotplug_io_size;
extern unsigned long pci_hotplug_mem_size; extern unsigned long pci_hotplug_mem_size;
/* Architecture specific versions may override these (weak) */ /* Architecture-specific versions may override these (weak) */
int pcibios_add_platform_entries(struct pci_dev *dev); int pcibios_add_platform_entries(struct pci_dev *dev);
void pcibios_disable_device(struct pci_dev *dev); void pcibios_disable_device(struct pci_dev *dev);
void pcibios_set_master(struct pci_dev *dev); void pcibios_set_master(struct pci_dev *dev);

1
include/linux/pci_hotplug.h
View file

@ -191,4 +191,3 @@ static inline int pci_get_hp_params(struct pci_dev *dev,
void pci_configure_slot(struct pci_dev *dev); void pci_configure_slot(struct pci_dev *dev);
#endif #endif

58
include/uapi/linux/pci_regs.h
View file

@ -13,10 +13,10 @@
* PCI to PCI Bridge Specification * PCI to PCI Bridge Specification
* PCI System Design Guide * PCI System Design Guide
* *
* For hypertransport information, please consult the following manuals * For HyperTransport information, please consult the following manuals
* from http://www.hypertransport.org * from http://www.hypertransport.org
* *
* The Hypertransport I/O Link Specification * The HyperTransport I/O Link Specification
*/ */
#ifndef LINUX_PCI_REGS_H #ifndef LINUX_PCI_REGS_H
@ -45,7 +45,7 @@
#define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
@ -205,7 +205,7 @@
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
#define PCI_CAP_ID_DBG 0x0A /* Debug port */ #define PCI_CAP_ID_DBG 0x0A /* Debug port */
#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
@ -321,7 +321,7 @@
#define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
/* MSI-X entry's format */ /* MSI-X Table entry format */
#define PCI_MSIX_ENTRY_SIZE 16 #define PCI_MSIX_ENTRY_SIZE 16
#define PCI_MSIX_ENTRY_LOWER_ADDR 0 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
#define PCI_MSIX_ENTRY_UPPER_ADDR 4 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
@ -407,8 +407,8 @@
/* PCI Bridge Subsystem ID registers */ /* PCI Bridge Subsystem ID registers */
#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */
#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */ #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */
/* PCI Express capability registers */ /* PCI Express capability registers */
@ -484,12 +484,12 @@
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */
#define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA 18 /* Link Status */
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
@ -593,7 +593,7 @@
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */ #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
@ -602,12 +602,12 @@
#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */ #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */ #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */ #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */ #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */ #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */ #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
@ -667,9 +667,9 @@
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
/* Multi ERR_COR Received */ /* Multi ERR_COR Received */
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
/* ERR_FATAL/NONFATAL Recevied */ /* ERR_FATAL/NONFATAL Received */
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
/* Multi ERR_FATAL/NONFATAL Recevied */ /* Multi ERR_FATAL/NONFATAL Received */
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
@ -678,7 +678,7 @@
/* Virtual Channel */ /* Virtual Channel */
#define PCI_VC_PORT_REG1 4 #define PCI_VC_PORT_REG1 4
#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */ #define PCI_VC_REG1_EVCC 0x7 /* extended VC count */
#define PCI_VC_PORT_REG2 8 #define PCI_VC_PORT_REG2 8
#define PCI_VC_REG2_32_PHASE 0x2 #define PCI_VC_REG2_32_PHASE 0x2
#define PCI_VC_REG2_64_PHASE 0x4 #define PCI_VC_REG2_64_PHASE 0x4
@ -711,7 +711,7 @@
#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
/* /*
* Hypertransport sub capability types * HyperTransport sub capability types
* *
* Unfortunately there are both 3 bit and 5 bit capability types defined * Unfortunately there are both 3 bit and 5 bit capability types defined
* in the HT spec, catering for that is a little messy. You probably don't * in the HT spec, catering for that is a little messy. You probably don't
@ -739,8 +739,8 @@
#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */
#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */
#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */
#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */
@ -777,14 +777,14 @@
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
#define PCI_EXT_CAP_PRI_SIZEOF 16 #define PCI_EXT_CAP_PRI_SIZEOF 16
/* PASID capability */ /* Process Address Space ID */
#define PCI_PASID_CAP 0x04 /* PASID feature register */ #define PCI_PASID_CAP 0x04 /* PASID feature register */
#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
#define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */ #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */
#define PCI_PASID_CTRL 0x06 /* PASID control register */ #define PCI_PASID_CTRL 0x06 /* PASID control register */
#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */
#define PCI_EXT_CAP_PASID_SIZEOF 8 #define PCI_EXT_CAP_PASID_SIZEOF 8
/* Single Root I/O Virtualization */ /* Single Root I/O Virtualization */
@ -839,22 +839,22 @@
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ #define PCI_ACS_CTRL 0x06 /* ACS Control Register */
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */ #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
/* sata capability */ /* SATA capability */
#define PCI_SATA_REGS 4 /* SATA REGs specifier */ #define PCI_SATA_REGS 4 /* SATA REGs specifier */
#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */
#define PCI_SATA_SIZEOF_SHORT 8 #define PCI_SATA_SIZEOF_SHORT 8
#define PCI_SATA_SIZEOF_LONG 16 #define PCI_SATA_SIZEOF_LONG 16
/* resizable BARs */ /* Resizable BARs */
#define PCI_REBAR_CTRL 8 /* control register */ #define PCI_REBAR_CTRL 8 /* control register */
#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
/* dynamic power allocation */ /* Dynamic Power Allocation */
#define PCI_DPA_CAP 4 /* capability register */ #define PCI_DPA_CAP 4 /* capability register */
#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */