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PCI/ACPI: Implement _HPX Type 3 Setting Record
The _HPX Type 3 Setting Record is intended to be more generic and allow configuration of settings not possible with Type 2 records. For example, firmware could ensure that the completion timeout value is set accordingly throughout the PCI tree. Implement support for _HPX Type 3 Setting Records, which were added in the ACPI 6.3 spec. Link: https://lore.kernel.org/lkml/20190208162414.3996-4-mr.nuke.me@gmail.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -124,10 +124,58 @@ struct hpp_type2 {
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u32 sec_unc_err_mask_or;
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};
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/*
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* _HPX PCI Express Setting Record (Type 3)
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*/
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struct hpx_type3 {
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u16 device_type;
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u16 function_type;
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u16 config_space_location;
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u16 pci_exp_cap_id;
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u16 pci_exp_cap_ver;
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u16 pci_exp_vendor_id;
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u16 dvsec_id;
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u16 dvsec_rev;
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u16 match_offset;
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u32 match_mask_and;
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u32 match_value;
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u16 reg_offset;
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u32 reg_mask_and;
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u32 reg_mask_or;
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};
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struct hotplug_program_ops {
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void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp);
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void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp);
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void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp);
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void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp);
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};
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enum hpx_type3_dev_type {
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HPX_TYPE_ENDPOINT = BIT(0),
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HPX_TYPE_LEG_END = BIT(1),
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HPX_TYPE_RC_END = BIT(2),
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HPX_TYPE_RC_EC = BIT(3),
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HPX_TYPE_ROOT_PORT = BIT(4),
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HPX_TYPE_UPSTREAM = BIT(5),
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HPX_TYPE_DOWNSTREAM = BIT(6),
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HPX_TYPE_PCI_BRIDGE = BIT(7),
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HPX_TYPE_PCIE_BRIDGE = BIT(8),
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};
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enum hpx_type3_fn_type {
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HPX_FN_NORMAL = BIT(0),
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HPX_FN_SRIOV_PHYS = BIT(1),
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HPX_FN_SRIOV_VIRT = BIT(2),
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};
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enum hpx_type3_cfg_loc {
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HPX_CFG_PCICFG = 0,
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HPX_CFG_PCIE_CAP = 1,
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HPX_CFG_PCIE_CAP_EXT = 2,
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HPX_CFG_VEND_CAP = 3,
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HPX_CFG_DVSEC = 4,
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HPX_CFG_MAX,
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};
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#ifdef CONFIG_ACPI
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