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MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.

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Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2009-05-13 15:59:55 -07:00 • committed by Ralf Baechle
parent 9cffd154cf
commit fbeda19f82
2 changed files with 5 additions and 1 deletions
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4
arch/mips/include/asm/cpu-features.h
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@ -234,4 +234,8 @@
#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits 0
#endif
#endif /* __ASM_CPU_FEATURES_H */