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Merge tag 'drm-intel-fixes-2016-05-02' of git://anongit.freedesktop.org/drm-intel into drm-fixes
i915 fixes for 4.6. A bit more than I'd like at this stage, but OTOH they're all stable material. * tag 'drm-intel-fixes-2016-05-02' of git://anongit.freedesktop.org/drm-intel: drm/i915: Make RPS EI/thresholds multiple of 25 on SNB-BDW drm/i915: Fake HDMI live status drm/i915: Fix eDP low vswing for Broadwell drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resume drm/i915: Fix system resume if PCI device remained enabled drm/i915: Avoid stalling on pending flips for legacy cursor updates
This commit is contained in:
commit
fca097169f
7 changed files with 69 additions and 15 deletions
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@ -792,7 +792,7 @@ static int i915_drm_resume(struct drm_device *dev)
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static int i915_drm_resume_early(struct drm_device *dev)
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static int i915_drm_resume_early(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = 0;
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int ret;
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/*
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/*
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* We have a resume ordering issue with the snd-hda driver also
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* We have a resume ordering issue with the snd-hda driver also
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@ -803,6 +803,36 @@ static int i915_drm_resume_early(struct drm_device *dev)
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* FIXME: This should be solved with a special hdmi sink device or
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* FIXME: This should be solved with a special hdmi sink device or
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* similar so that power domains can be employed.
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* similar so that power domains can be employed.
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*/
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*/
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/*
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* Note that we need to set the power state explicitly, since we
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* powered off the device during freeze and the PCI core won't power
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* it back up for us during thaw. Powering off the device during
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* freeze is not a hard requirement though, and during the
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* suspend/resume phases the PCI core makes sure we get here with the
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* device powered on. So in case we change our freeze logic and keep
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* the device powered we can also remove the following set power state
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* call.
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*/
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ret = pci_set_power_state(dev->pdev, PCI_D0);
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if (ret) {
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DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
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goto out;
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}
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/*
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* Note that pci_enable_device() first enables any parent bridge
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* device and only then sets the power state for this device. The
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* bridge enabling is a nop though, since bridge devices are resumed
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* first. The order of enabling power and enabling the device is
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* imposed by the PCI core as described above, so here we preserve the
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* same order for the freeze/thaw phases.
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*
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* TODO: eventually we should remove pci_disable_device() /
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* pci_enable_enable_device() from suspend/resume. Due to how they
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* depend on the device enable refcount we can't anyway depend on them
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* disabling/enabling the device.
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*/
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if (pci_enable_device(dev->pdev)) {
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if (pci_enable_device(dev->pdev)) {
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ret = -EIO;
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ret = -EIO;
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goto out;
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goto out;
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@ -2907,7 +2907,14 @@ enum skl_disp_power_wells {
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#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
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#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
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#define BXT_RP_STATE_CAP _MMIO(0x138170)
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#define BXT_RP_STATE_CAP _MMIO(0x138170)
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#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
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/*
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* Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
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* 8300) freezing up around GPU hangs. Looks as if even
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* scheduling/timer interrupts start misbehaving if the RPS
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* EI/thresholds are "bad", leading to a very sluggish or even
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* frozen machine.
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*/
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#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
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#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
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#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
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#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
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#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
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#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
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#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
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@ -443,9 +443,17 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
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} else if (IS_BROADWELL(dev_priv)) {
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} else if (IS_BROADWELL(dev_priv)) {
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ddi_translations_fdi = bdw_ddi_translations_fdi;
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ddi_translations_fdi = bdw_ddi_translations_fdi;
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ddi_translations_dp = bdw_ddi_translations_dp;
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ddi_translations_dp = bdw_ddi_translations_dp;
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ddi_translations_edp = bdw_ddi_translations_edp;
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if (dev_priv->edp_low_vswing) {
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ddi_translations_edp = bdw_ddi_translations_edp;
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n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
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} else {
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ddi_translations_edp = bdw_ddi_translations_dp;
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n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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}
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ddi_translations_hdmi = bdw_ddi_translations_hdmi;
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ddi_translations_hdmi = bdw_ddi_translations_hdmi;
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n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
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n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
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n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
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hdmi_default_entry = 7;
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hdmi_default_entry = 7;
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@ -3201,12 +3209,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
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intel_ddi_clock_get(encoder, pipe_config);
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intel_ddi_clock_get(encoder, pipe_config);
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}
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}
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static void intel_ddi_destroy(struct drm_encoder *encoder)
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{
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/* HDMI has nothing special to destroy, so we can go with this. */
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intel_dp_encoder_destroy(encoder);
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}
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static bool intel_ddi_compute_config(struct intel_encoder *encoder,
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static bool intel_ddi_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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struct intel_crtc_state *pipe_config)
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{
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{
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@ -3225,7 +3227,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
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}
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}
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static const struct drm_encoder_funcs intel_ddi_funcs = {
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static const struct drm_encoder_funcs intel_ddi_funcs = {
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.destroy = intel_ddi_destroy,
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.reset = intel_dp_encoder_reset,
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.destroy = intel_dp_encoder_destroy,
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};
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};
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static struct intel_connector *
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static struct intel_connector *
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@ -3324,6 +3327,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
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intel_encoder->post_disable = intel_ddi_post_disable;
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intel_encoder->post_disable = intel_ddi_post_disable;
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intel_encoder->get_hw_state = intel_ddi_get_hw_state;
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intel_encoder->get_hw_state = intel_ddi_get_hw_state;
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intel_encoder->get_config = intel_ddi_get_config;
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intel_encoder->get_config = intel_ddi_get_config;
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intel_encoder->suspend = intel_dp_encoder_suspend;
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intel_dig_port->port = port;
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intel_dig_port->port = port;
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intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
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intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
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@ -13351,6 +13351,9 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
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}
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}
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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if (state->legacy_cursor_update)
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continue;
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ret = intel_crtc_wait_for_pending_flips(crtc);
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ret = intel_crtc_wait_for_pending_flips(crtc);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -4898,7 +4898,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
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kfree(intel_dig_port);
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kfree(intel_dig_port);
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}
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}
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static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
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{
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
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struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
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@ -4940,7 +4940,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
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edp_panel_vdd_schedule_off(intel_dp);
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edp_panel_vdd_schedule_off(intel_dp);
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}
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}
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static void intel_dp_encoder_reset(struct drm_encoder *encoder)
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void intel_dp_encoder_reset(struct drm_encoder *encoder)
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{
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{
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struct intel_dp *intel_dp;
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struct intel_dp *intel_dp;
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@ -1238,6 +1238,8 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_encoder_reset(struct drm_encoder *encoder);
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_destroy(struct drm_encoder *encoder);
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void intel_dp_encoder_destroy(struct drm_encoder *encoder);
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int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
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int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
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bool intel_dp_compute_config(struct intel_encoder *encoder,
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bool intel_dp_compute_config(struct intel_encoder *encoder,
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@ -1415,8 +1415,16 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
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hdmi_to_dig_port(intel_hdmi));
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hdmi_to_dig_port(intel_hdmi));
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}
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}
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if (!live_status)
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if (!live_status) {
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DRM_DEBUG_KMS("Live status not up!");
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DRM_DEBUG_KMS("HDMI live status down\n");
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/*
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* Live status register is not reliable on all intel platforms.
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* So consider live_status only for certain platforms, for
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* others, read EDID to determine presence of sink.
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*/
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if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
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live_status = true;
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}
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intel_hdmi_unset_edid(connector);
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intel_hdmi_unset_edid(connector);
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