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net/mlx5: ODP support for XRC transport is not enabled by default in FW

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ODP support for XRC transport is not enabled by default in FW, so we need
separate ODP checks to enable/disable it.

While that, rewrite the set of ODP SRQ support capabilities in way that
tests each field separately for clearness, which is not needed for current
FW, but better to have it separated.

Signed-off-by: Moni Shoua <monis@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Moni Shoua 2019-02-25 08:54:39 +02:00 • committed by Jason Gunthorpe
parent bc5add0976
commit fca22e7e59
1 changed files with 21 additions and 14 deletions
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35
drivers/net/ethernet/mellanox/mlx5/core/main.c
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@ -465,6 +465,7 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
void *set_hca_cap; void *set_hca_cap;
void *set_ctx; void *set_ctx;
int set_sz; int set_sz;
bool do_set = false;
int err; int err;
if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
@ -475,11 +476,6 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
if (err) if (err)
return err; return err;
if (!(MLX5_CAP_ODP_MAX(dev, ud_odp_caps.srq_receive) ||
MLX5_CAP_ODP_MAX(dev, rc_odp_caps.srq_receive) ||
MLX5_CAP_ODP_MAX(dev, xrc_odp_caps.srq_receive)))
return 0;
set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
set_ctx = kzalloc(set_sz, GFP_KERNEL); set_ctx = kzalloc(set_sz, GFP_KERNEL);
if (!set_ctx) if (!set_ctx)
@ -489,19 +485,30 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
MLX5_ST_SZ_BYTES(odp_cap)); MLX5_ST_SZ_BYTES(odp_cap));
/* set ODP SRQ support for RC/UD and XRC transports */ #define ODP_CAP_SET_MAX(dev, field) \
MLX5_SET(odp_cap, set_hca_cap, ud_odp_caps.srq_receive, do { \
MLX5_CAP_ODP_MAX(dev, ud_odp_caps.srq_receive)); u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
if (_res) { \
do_set = true; \
MLX5_SET(odp_cap, set_hca_cap, field, _res); \
} \
} while (0)
MLX5_SET(odp_cap, set_hca_cap, rc_odp_caps.srq_receive, ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
MLX5_CAP_ODP_MAX(dev, rc_odp_caps.srq_receive)); ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
MLX5_SET(odp_cap, set_hca_cap, xrc_odp_caps.srq_receive, if (do_set)
MLX5_CAP_ODP_MAX(dev, xrc_odp_caps.srq_receive)); err = set_caps(dev, set_ctx, set_sz,
MLX5_SET_HCA_CAP_OP_MOD_ODP);
err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ODP);
kfree(set_ctx); kfree(set_ctx);
return err; return err;
} }