From fea53546be574f2e357fa53f4a582788b20f283c Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Thu, 17 Nov 2022 07:10:35 +0100 Subject: [PATCH] ARM: 9274/1: Add hwcap for Speculative Store Bypassing Safe Speculative Store Bypassing Safe(FEAT_SSBS) is a feature present in AArch32 state for Armv8 and is represented by ID_PFR2_EL1.SSBS identification register. This feature denotes the presence of PSTATE.ssbs bit and hence adding a hwcap will enable the userspace to check it before trying to set/unset this PSTATE. This commit adds the ID feature bit detection, and uses elf_hwcap2 accordingly. Reviewed-by: Linus Walleij Signed-off-by: Amit Daniel Kachhap Signed-off-by: Russell King (Oracle) --- arch/arm/include/uapi/asm/hwcap.h | 1 + arch/arm/kernel/setup.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h index bc9e7d318e25..6b2023e39b6f 100644 --- a/arch/arm/include/uapi/asm/hwcap.h +++ b/arch/arm/include/uapi/asm/hwcap.h @@ -44,5 +44,6 @@ #define HWCAP2_SHA2 (1 << 3) #define HWCAP2_CRC32 (1 << 4) #define HWCAP2_SB (1 << 5) +#define HWCAP2_SSBS (1 << 6) #endif /* _UAPI__ASMARM_HWCAP_H */ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 979612add87a..4ec3ec32d830 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -451,6 +451,7 @@ static void __init cpuid_init_hwcaps(void) int block; u32 isar5; u32 isar6; + u32 pfr2; if (cpu_architecture() < CPU_ARCH_ARMv7) return; @@ -492,6 +493,12 @@ static void __init cpuid_init_hwcaps(void) block = cpuid_feature_extract_field(isar6, 12); if (block >= 1) elf_hwcap2 |= HWCAP2_SB; + + /* Check for Speculative Store Bypassing control */ + pfr2 = read_cpuid_ext(CPUID_EXT_PFR2); + block = cpuid_feature_extract_field(pfr2, 4); + if (block >= 1) + elf_hwcap2 |= HWCAP2_SSBS; } static void __init elf_hwcap_fixup(void) @@ -1272,6 +1279,7 @@ static const char *hwcap2_str[] = { "sha2", "crc32", "sb", + "ssbs", NULL };