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drm/amdgpu: use static mmio offset for NV mailbox

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what:
with the new "req_init_data" handshake we need to use mailbox
before do IP discovery, so in mxgpu_nv.c file the original
SOC15_REG method won'twork because that depends on IP discovery
complete first.

how:
so the solution is to always use static MMIO offset for NV+ mailbox
registers.
HW team confirm us all MAILBOX registers will be at the same
offset for all ASICs, no IP discovery needed for those registers

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2020-03-04 23:46:45 +08:00 • committed by Alex Deucher
parent aa53bc2edb
commit ff1f03a7b8
2 changed files with 38 additions and 32 deletions
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18
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
View file

@ -59,7 +59,21 @@ int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);
int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);
void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);
#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4)
#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4 + 1)
#define mmMAILBOX_CONTROL 0xE5E
#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1)
#define mmMAILBOX_MSGBUF_TRN_DW0 0xE56
#define mmMAILBOX_MSGBUF_TRN_DW1 0xE57
#define mmMAILBOX_MSGBUF_TRN_DW2 0xE58
#define mmMAILBOX_MSGBUF_TRN_DW3 0xE59
#define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A
#define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B
#define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C
#define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D
#define mmMAILBOX_INT_CNTL 0xE5F
#endif