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drm/arm/malidp: Split malidp interrupt initialization functions.

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Malidp uses two interrupts ie 1. se_irq - used for memory writeback.
 and 2. de_irq - used for display output.
Extract the hardware initialization part from malidp interrupt registration
ie (malidp_de_irq_init()/ malidp_se_irq_init()) into a separate function
(ie malidp_de_irq_hw_init()/malidp_se_irq_hw_init())
which will be later invoked from runtime_pm_resume function when it needs
to re-enable the interrupts.

Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
This commit is contained in:
Ayan Kumar Halder 2018-05-15 17:04:16 +01:00 • committed by Liviu Dudau
parent 62862cfbb1
commit ff8fc26a76
2 changed files with 31 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

38
drivers/gpu/drm/arm/malidp_hw.c
View file

@ -967,6 +967,23 @@ static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev)
{
/* ensure interrupts are disabled */
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
/* first enable the DC block IRQs */
malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
hwdev->hw->map.dc_irq_map.irq_mask);
/* now enable the DE block IRQs */
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->hw->map.de_irq_map.irq_mask);
}
int malidp_de_irq_init(struct drm_device *drm, int irq) int malidp_de_irq_init(struct drm_device *drm, int irq)
{ {
struct malidp_drm *malidp = drm->dev_private; struct malidp_drm *malidp = drm->dev_private;
@ -987,13 +1004,7 @@ int malidp_de_irq_init(struct drm_device *drm, int irq)
return ret; return ret;
} }
/* first enable the DC block IRQs */ malidp_de_irq_hw_init(hwdev);
malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
hwdev->hw->map.dc_irq_map.irq_mask);
/* now enable the DE block IRQs */
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->hw->map.de_irq_map.irq_mask);
return 0; return 0;
} }
@ -1069,6 +1080,16 @@ static irqreturn_t malidp_se_irq(int irq, void *arg)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev)
{
/* ensure interrupts are disabled */
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
hwdev->hw->map.se_irq_map.irq_mask);
}
static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg) static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
{ {
return IRQ_HANDLED; return IRQ_HANDLED;
@ -1093,8 +1114,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq)
} }
hwdev->mw_state = MW_NOT_ENABLED; hwdev->mw_state = MW_NOT_ENABLED;
malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, malidp_se_irq_hw_init(hwdev);
hwdev->hw->map.se_irq_map.irq_mask);
return 0; return 0;
} }

2
drivers/gpu/drm/arm/malidp_hw.h
View file

@ -302,6 +302,8 @@ static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev,
} }
int malidp_de_irq_init(struct drm_device *drm, int irq); int malidp_de_irq_init(struct drm_device *drm, int irq);
void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev);
void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev);
void malidp_de_irq_fini(struct malidp_hw_device *hwdev); void malidp_de_irq_fini(struct malidp_hw_device *hwdev);
int malidp_se_irq_init(struct drm_device *drm, int irq); int malidp_se_irq_init(struct drm_device *drm, int irq);
void malidp_se_irq_fini(struct malidp_hw_device *hwdev); void malidp_se_irq_fini(struct malidp_hw_device *hwdev);