2 commits

Author	SHA1	Message	Date
Jun Nie	8d9a0860b7	clk: zx: reform pll config info to ease code extension ... Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2016-09-14 13:48:32 -07:00
Jun Nie	4599dd2c92	clk: zx: Add audio div clock method for zx296702 ... Add SPDIF/I2S divider clock method for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2015-07-28 11:59:34 -07:00

Renamed from drivers/clk/zte/clk-pll.c (Browse further)