4 commits

Author	SHA1	Message	Date
Mika Westerberg	ecc8995363	pinctrl: broxton: Use correct PADCFGLOCK offset ... PADCFGLOCK (and PADCFGLOCK_TX) offset in Broxton actually starts at 0x060 and not 0x090 as used in the driver. Fix it to use the correct offset. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2017-01-11 13:47:11 +01:00
Tan Jui Nee	0c3013bbe1	pinctrl/broxton: enable platform device in the absence of ACPI enumeration ... This is to cater the need for non-ACPI system whereby a platform device has to be created in order to bind with the Apollo Lake Pinctrl GPIO platform driver. Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2016-06-15 08:37:42 +02:00
Qipeng Zha	618a919b4c	pinctrl: intel: fix bug of register offset calculation ... The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS, GPI_IE, are not 24 for Broxton, Add a parameter to allow different platform to set correct value. Signed-off-by: Qi Zheng <qi.zheng@intel.com> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2015-12-10 23:01:41 +01:00
Mika Westerberg	ee1a6ca43d	pinctrl: intel: Add Intel Broxton pin controller support ... This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2015-10-27 13:32:13 +01:00