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87161ccdc6
Since 3.6.0-rc1, We are getting many messages like: WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260() Modules linked in: Call Trace: [<ffffffff814cb698>] dump_stack+0x8/0x34 [<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8 [<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260 [<ffffffff81187f38>] irq_create_mapping+0xd0/0x220 [<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158 [<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40 . . . Both the CIU and GPIO interrupt domains were somewhat screwed up. For the CIU domain, we need to call irq_domain_associate() for each of the preassigned irq numbers. For the GPIO domain, we were applying the register bit offset in octeon_irq_gpio_xlat, but it should be done in octeon_irq_gpio_map instead. Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they don't get used by the other domains. Remove unused OCTEON_IRQ_* symbols. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#ifndef __OCTEON_IRQ_H__
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#define __OCTEON_IRQ_H__
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#define NR_IRQS OCTEON_IRQ_LAST
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#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
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enum octeon_irq {
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/* 1 - 8 represent the 8 MIPS standard interrupt sources */
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OCTEON_IRQ_SW0 = 1,
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OCTEON_IRQ_SW1,
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/* CIU0, CUI2, CIU4 are 3, 4, 5 */
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OCTEON_IRQ_5 = 6,
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OCTEON_IRQ_PERF,
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OCTEON_IRQ_TIMER,
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/* sources in CIU_INTX_EN0 */
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OCTEON_IRQ_WORKQ0,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
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OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
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OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
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OCTEON_IRQ_MBOX1,
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OCTEON_IRQ_PCI_INT0,
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OCTEON_IRQ_PCI_INT1,
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OCTEON_IRQ_PCI_INT2,
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OCTEON_IRQ_PCI_INT3,
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OCTEON_IRQ_PCI_MSI0,
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OCTEON_IRQ_PCI_MSI1,
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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OCTEON_IRQ_TIMER2,
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OCTEON_IRQ_TIMER3,
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OCTEON_IRQ_USB0,
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OCTEON_IRQ_USB1,
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OCTEON_IRQ_BOOTDMA,
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#ifndef CONFIG_PCI_MSI
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OCTEON_IRQ_LAST = 127
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#endif
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};
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#ifdef CONFIG_PCI_MSI
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/* 256 - 511 represent the MSI interrupts 0-255 */
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#define OCTEON_IRQ_MSI_BIT0 (256)
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#endif
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#endif
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