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During a device tree overlay pre-apply notification, the check for child FPGA regions can happen slightly earlier. This saves us from allocating the FPGA image info that just gets thrown away. This is a baby step in refactoring the FPGA region code to separate out common FPGA region code from FPGA region Device Tree overlay support. Signed-off-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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altera-cvp.c | ||
altera-fpga2sdram.c | ||
altera-freeze-bridge.c | ||
altera-hps2fpga.c | ||
altera-pr-ip-core-plat.c | ||
altera-pr-ip-core.c | ||
altera-ps-spi.c | ||
fpga-bridge.c | ||
fpga-mgr.c | ||
fpga-region.c | ||
ice40-spi.c | ||
Kconfig | ||
Makefile | ||
socfpga-a10.c | ||
socfpga.c | ||
ts73xx-fpga.c | ||
xilinx-pr-decoupler.c | ||
xilinx-spi.c | ||
zynq-fpga.c |