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https://github.com/Fishwaldo/Star64_linux.git
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2bc3fc877a
Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
51 lines
916 B
C
51 lines
916 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_TIMEX_H
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#define _ASM_RISCV_TIMEX_H
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#include <asm/csr.h>
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typedef unsigned long cycles_t;
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static inline cycles_t get_cycles(void)
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{
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return csr_read(CSR_TIME);
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}
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#define get_cycles get_cycles
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static inline u32 get_cycles_hi(void)
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{
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return csr_read(CSR_TIMEH);
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}
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#define get_cycles_hi get_cycles_hi
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#ifdef CONFIG_64BIT
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static inline u64 get_cycles64(void)
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{
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return get_cycles();
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}
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#else /* CONFIG_64BIT */
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static inline u64 get_cycles64(void)
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{
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u32 hi, lo;
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do {
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hi = get_cycles_hi();
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lo = get_cycles();
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} while (hi != get_cycles_hi());
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return ((u64)hi << 32) | lo;
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}
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#endif /* CONFIG_64BIT */
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#define ARCH_HAS_READ_CURRENT_TIMER
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static inline int read_current_timer(unsigned long *timer_val)
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{
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*timer_val = get_cycles();
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return 0;
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}
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#endif /* _ASM_RISCV_TIMEX_H */
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