mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-05-10 01:03:58 +00:00
This is a methodical transition of the driver from phylib
to phylink, following the guidelines from sfp-phylink.rst.
The MAC register configurations based on interface mode
were moved from the probing path to the mac_config() hook.
MAC enable and disable commands (enabling Rx and Tx paths
at MAC level) were also extracted and assigned to their
corresponding phylink hooks.
As part of the migration to phylink, the serdes configuration
from the driver was offloaded to the PCS_LYNX module,
introduced in commit 0da4c3d393
("net: phy: add Lynx PCS module"),
the PCS_LYNX module being a mandatory component required to
make the enetc driver work with phylink.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.cionei@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
408 lines
10 KiB
C
408 lines
10 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2017-2019 NXP */
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/skbuff.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/phylink.h>
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#include <linux/dim.h>
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#include "enetc_hw.h"
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#define ENETC_MAC_MAXFRM_SIZE 9600
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#define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \
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(ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN))
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struct enetc_tx_swbd {
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struct sk_buff *skb;
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dma_addr_t dma;
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u16 len;
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u8 is_dma_page:1;
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u8 check_wb:1;
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u8 do_tstamp:1;
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};
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#define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE
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#define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */
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#define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */
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#define ENETC_RXB_DMA_SIZE \
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(SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD)
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struct enetc_rx_swbd {
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dma_addr_t dma;
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struct page *page;
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u16 page_offset;
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};
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struct enetc_ring_stats {
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unsigned int packets;
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unsigned int bytes;
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unsigned int rx_alloc_errs;
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};
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#define ENETC_RX_RING_DEFAULT_SIZE 512
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#define ENETC_TX_RING_DEFAULT_SIZE 256
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#define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2)
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struct enetc_bdr {
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struct device *dev; /* for DMA mapping */
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struct net_device *ndev;
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void *bd_base; /* points to Rx or Tx BD ring */
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union {
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void __iomem *tpir;
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void __iomem *rcir;
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};
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u16 index;
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int bd_count; /* # of BDs */
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int next_to_use;
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int next_to_clean;
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union {
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struct enetc_tx_swbd *tx_swbd;
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struct enetc_rx_swbd *rx_swbd;
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};
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union {
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void __iomem *tcir; /* Tx */
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int next_to_alloc; /* Rx */
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};
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void __iomem *idr; /* Interrupt Detect Register pointer */
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struct enetc_ring_stats stats;
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dma_addr_t bd_dma_base;
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u8 tsd_enable; /* Time specific departure */
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bool ext_en; /* enable h/w descriptor extensions */
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} ____cacheline_aligned_in_smp;
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static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i)
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{
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if (unlikely(++*i == bdr->bd_count))
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*i = 0;
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}
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static inline int enetc_bd_unused(struct enetc_bdr *bdr)
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{
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if (bdr->next_to_clean > bdr->next_to_use)
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return bdr->next_to_clean - bdr->next_to_use - 1;
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return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
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}
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/* Control BD ring */
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#define ENETC_CBDR_DEFAULT_SIZE 64
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struct enetc_cbdr {
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void *bd_base; /* points to Rx or Tx BD ring */
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void __iomem *pir;
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void __iomem *cir;
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int bd_count; /* # of BDs */
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int next_to_use;
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int next_to_clean;
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dma_addr_t bd_dma_base;
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};
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#define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i]))
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static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i)
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{
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int hw_idx = i;
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#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
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if (rx_ring->ext_en)
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hw_idx = 2 * i;
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#endif
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return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
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}
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static inline union enetc_rx_bd *enetc_rxbd_next(struct enetc_bdr *rx_ring,
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union enetc_rx_bd *rxbd,
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int i)
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{
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rxbd++;
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#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
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if (rx_ring->ext_en)
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rxbd++;
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#endif
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if (unlikely(++i == rx_ring->bd_count))
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rxbd = rx_ring->bd_base;
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return rxbd;
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}
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static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd)
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{
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return ++rxbd;
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}
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struct enetc_msg_swbd {
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void *vaddr;
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dma_addr_t dma;
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int size;
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};
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#define ENETC_REV1 0x1
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enum enetc_errata {
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ENETC_ERR_TXCSUM = BIT(0),
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ENETC_ERR_VLAN_ISOL = BIT(1),
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ENETC_ERR_UCMCSWP = BIT(2),
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};
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#define ENETC_SI_F_QBV BIT(0)
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#define ENETC_SI_F_PSFP BIT(1)
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/* PCI IEP device data */
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struct enetc_si {
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struct pci_dev *pdev;
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struct enetc_hw hw;
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enum enetc_errata errata;
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struct net_device *ndev; /* back ref. */
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struct enetc_cbdr cbd_ring;
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int num_rx_rings; /* how many rings are available in the SI */
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int num_tx_rings;
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int num_fs_entries;
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int num_rss; /* number of RSS buckets */
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unsigned short pad;
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int hw_features;
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};
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#define ENETC_SI_ALIGN 32
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static inline void *enetc_si_priv(const struct enetc_si *si)
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{
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return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN);
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}
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static inline bool enetc_si_is_pf(struct enetc_si *si)
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{
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return !!(si->hw.port);
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}
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#define ENETC_MAX_NUM_TXQS 8
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#define ENETC_INT_NAME_MAX (IFNAMSIZ + 8)
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struct enetc_int_vector {
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void __iomem *rbier;
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void __iomem *tbier_base;
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void __iomem *ricr1;
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unsigned long tx_rings_map;
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int count_tx_rings;
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u32 rx_ictt;
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u16 comp_cnt;
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bool rx_dim_en, rx_napi_work;
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struct napi_struct napi ____cacheline_aligned_in_smp;
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struct dim rx_dim ____cacheline_aligned_in_smp;
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char name[ENETC_INT_NAME_MAX];
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struct enetc_bdr rx_ring;
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struct enetc_bdr tx_ring[];
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} ____cacheline_aligned_in_smp;
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struct enetc_cls_rule {
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struct ethtool_rx_flow_spec fs;
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int used;
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};
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#define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */
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struct psfp_cap {
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u32 max_streamid;
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u32 max_psfp_filter;
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u32 max_psfp_gate;
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u32 max_psfp_gatelist;
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u32 max_psfp_meter;
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};
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/* TODO: more hardware offloads */
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enum enetc_active_offloads {
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ENETC_F_RX_TSTAMP = BIT(0),
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ENETC_F_TX_TSTAMP = BIT(1),
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ENETC_F_QBV = BIT(2),
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ENETC_F_QCI = BIT(3),
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};
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/* interrupt coalescing modes */
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enum enetc_ic_mode {
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/* one interrupt per frame */
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ENETC_IC_NONE = 0,
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/* activated when int coalescing time is set to a non-0 value */
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ENETC_IC_RX_MANUAL = BIT(0),
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ENETC_IC_TX_MANUAL = BIT(1),
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/* use dynamic interrupt moderation */
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ENETC_IC_RX_ADAPTIVE = BIT(2),
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};
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#define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2)
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#define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2)
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#define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600)
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struct enetc_ndev_priv {
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struct net_device *ndev;
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struct device *dev; /* dma-mapping device */
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struct enetc_si *si;
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int bdr_int_num; /* number of Rx/Tx ring interrupts */
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struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT];
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u16 num_rx_rings, num_tx_rings;
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u16 rx_bd_count, tx_bd_count;
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u16 msg_enable;
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int active_offloads;
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u32 speed; /* store speed for compare update pspeed */
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struct enetc_bdr *tx_ring[16];
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struct enetc_bdr *rx_ring[16];
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struct enetc_cls_rule *cls_rules;
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struct psfp_cap psfp_cap;
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struct phylink *phylink;
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int ic_mode;
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u32 tx_ictt;
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};
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/* Messaging */
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/* VF-PF set primary MAC address message format */
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struct enetc_msg_cmd_set_primary_mac {
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struct enetc_msg_cmd_header header;
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struct sockaddr mac;
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};
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#define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i]))
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#define ENETC_CBDR_TIMEOUT 1000 /* usecs */
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/* PTP driver exports */
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extern int enetc_phc_index;
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/* SI common */
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int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
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void enetc_pci_remove(struct pci_dev *pdev);
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int enetc_alloc_msix(struct enetc_ndev_priv *priv);
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void enetc_free_msix(struct enetc_ndev_priv *priv);
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void enetc_get_si_caps(struct enetc_si *si);
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void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
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int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
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void enetc_free_si_resources(struct enetc_ndev_priv *priv);
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int enetc_open(struct net_device *ndev);
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int enetc_close(struct net_device *ndev);
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void enetc_start(struct net_device *ndev);
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void enetc_stop(struct net_device *ndev);
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netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev);
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struct net_device_stats *enetc_get_stats(struct net_device *ndev);
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int enetc_set_features(struct net_device *ndev,
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netdev_features_t features);
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int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd);
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int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type,
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void *type_data);
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/* ethtool */
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void enetc_set_ethtool_ops(struct net_device *ndev);
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/* control buffer descriptor ring (CBDR) */
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int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
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char *mac_addr, int si_map);
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int enetc_clear_mac_flt_entry(struct enetc_si *si, int index);
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int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
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int index);
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void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes);
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int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count);
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int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count);
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int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd);
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#ifdef CONFIG_FSL_ENETC_QOS
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int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data);
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void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed);
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int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
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int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data);
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int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
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void *cb_priv);
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int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data);
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int enetc_psfp_init(struct enetc_ndev_priv *priv);
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int enetc_psfp_clean(struct enetc_ndev_priv *priv);
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static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv)
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{
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u32 reg;
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reg = enetc_port_rd(&priv->si->hw, ENETC_PSIDCAPR);
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priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK;
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/* Port stream filter capability */
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reg = enetc_port_rd(&priv->si->hw, ENETC_PSFCAPR);
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priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK;
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/* Port stream gate capability */
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reg = enetc_port_rd(&priv->si->hw, ENETC_PSGCAPR);
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priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK);
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priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16;
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/* Port flow meter capability */
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reg = enetc_port_rd(&priv->si->hw, ENETC_PFMCAPR);
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priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK;
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}
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static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
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{
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struct enetc_hw *hw = &priv->si->hw;
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int err;
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enetc_get_max_cap(priv);
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err = enetc_psfp_init(priv);
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if (err)
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return err;
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enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) |
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ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS |
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ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC);
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return 0;
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}
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static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
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{
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struct enetc_hw *hw = &priv->si->hw;
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int err;
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err = enetc_psfp_clean(priv);
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if (err)
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return err;
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enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) &
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~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS &
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~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC);
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memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap));
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return 0;
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}
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#else
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#define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP
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#define enetc_sched_speed_set(priv, speed) (void)0
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#define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP
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#define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP
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#define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP
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#define enetc_setup_tc_block_cb NULL
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#define enetc_get_max_cap(p) \
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memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap))
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static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
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{
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return 0;
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}
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static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
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{
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return 0;
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}
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#endif
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