Alex Deucher 3e10f3196b drm/amdgpu/display: switch udelay to msleep ... We may need to sleep for up to 80ms (8ms per each of up to 10 loop iterations): /* First DPCD read after VDD ON can fail if the particular board * does not have HPD pin wired correctly. So if DPCD read fails, * which it should never happen, retry a few times. Target worst * case scenario of 80 ms. */ Switch udelay to msleep to avoid limits on arm. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-25 12:08:46 -05:00
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amdgpu_dm	Merge branch 'drm-next' into drm-next-5.3	2019-06-25 08:42:25 -05:00
dc	drm/amdgpu/display: switch udelay to msleep	2019-06-25 12:08:46 -05:00
include	drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy	2019-06-22 09:34:13 -05:00
modules	Merge branch 'drm-next' into drm-next-5.3	2019-06-25 08:42:25 -05:00
Kconfig	drm/amd/display: enable DSC support by default	2019-06-22 09:34:08 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00