Star64_linux/drivers/pci/controller/dwc
Rob Herring 441e48fdf0 PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.

Link: https://lore.kernel.org/r/20200821035420.380495-36-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
2020-09-10 16:50:53 +01:00
..
Kconfig Merge branch 'remotes/lorenzo/pci/dwc' 2020-06-04 12:59:15 -05:00
Makefile PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver 2020-06-04 10:03:18 +01:00
pci-dra7xx.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pci-exynos.c PCI: dwc: exynos: Use pci_ops for root config space accessors 2020-09-08 16:37:02 +01:00
pci-imx6.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pci-keystone.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pci-layerscape-ep.c PCI: Add PCI_STD_NUM_BARS for the number of standard BARs 2019-10-14 10:22:26 -05:00
pci-layerscape.c PCI: layerscape: Add LS1028a support 2019-11-08 10:45:00 +00:00
pci-meson.c PCI: dwc/meson: Rework PCI config and DW port logic register accesses 2020-09-08 16:37:02 +01:00
pcie-al.c PCI: dwc: Remove storing of PCI resources 2020-09-08 16:37:02 +01:00
pcie-armada8k.c Merge branch 'pci/irq-error' 2020-08-05 18:24:22 -05:00
pcie-artpec6.c PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() 2020-09-08 16:37:02 +01:00
pcie-designware-ep.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-designware-host.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-designware-plat.c PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() 2020-09-08 16:37:02 +01:00
pcie-designware.c PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code 2020-09-10 16:50:53 +01:00
pcie-designware.h PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-hisi.c PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driver 2020-07-27 17:06:32 +01:00
pcie-histb.c PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() 2020-09-08 16:37:02 +01:00
pcie-intel-gw.c PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code 2020-09-10 16:50:53 +01:00
pcie-kirin.c PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() 2020-09-08 16:37:02 +01:00
pcie-qcom.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-spear13xx.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-tegra194.c PCI: dwc: Centralize link gen setting 2020-09-10 16:50:54 +01:00
pcie-uniphier-ep.c PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver 2020-06-04 10:03:18 +01:00
pcie-uniphier.c PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() 2020-09-08 16:37:02 +01:00