Kenneth Feng 597292eb73 drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss ... enable fw ctf, apcc dfll and gfx ss on navi10. fw ctf: when the fw ctf is triggered, the gfx and soc power domain are shut down. fan speed is boosted to the maximum. gfx ss: hardware feature, sanity check has been done. apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled. no need to do further check since the gfx hardware control the frequency once a pcc signal comes. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-16 14:49:57 -05:00
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hwmgr	drm/amdgpu: remove memset after kzalloc	2019-07-16 13:09:05 -05:00
inc	drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu	2019-07-16 13:08:23 -05:00
smumgr	drm/amdgpu: remove memset after kzalloc	2019-07-16 13:09:05 -05:00
amd_powerplay.c	drm/amd/powerplay: fix semicolon code style issue	2019-03-19 15:04:03 -05:00
amdgpu_smu.c	drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu	2019-07-16 13:08:23 -05:00
Makefile	drm/amd/powerplay: introduce the navi10 pptable implementation	2019-06-21 18:59:24 -05:00
navi10_ppt.c	drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss	2019-07-16 14:49:57 -05:00
navi10_ppt.h	drm/amd/powerplay: introduce the navi10 pptable implementation	2019-06-21 18:59:24 -05:00
smu_v11_0.c	drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq	2019-07-08 13:56:11 -05:00
vega20_ppt.c	drm/amd/powerplay: vega20: fix uninitialized variable use	2019-07-08 13:56:39 -05:00
vega20_ppt.h	drm/amd/powerplay: simplified od_settings for each asic	2019-06-21 18:59:32 -05:00