Hawking Zhang 73c86d628d drm/amdgpu: fix modprobe failure for uvd_4/5/6 ... For uvd_4/5/6, amdgpu driver will only power on them when there are jobs assigned to decode/enc rings.uvd_4/5/6 dpm was broken since amdgpu_dpm_set_powergating_by_smu only covers gfx block. The change would add more IP block support in amdgpu_dpm_set_powergating_by_smu For GFX/UVD/VCN/VCE, if the new SMU driver is supported, invoke new power gate helper function smu_dpm_set_power_gate, otherwise, fallback to legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks always invoke legacy powerplay helper function. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-24 09:29:59 -05:00
..
amdgpu.h	drm/amdgpu: drop unused df init callback	2019-06-22 09:34:14 -05:00
amdgpu_acp.c
amdgpu_acp.h
amdgpu_acpi.c
amdgpu_afmt.c
amdgpu_amdkfd.c
amdgpu_amdkfd.h
amdgpu_amdkfd_fence.c
amdgpu_amdkfd_gfx_v7.c
amdgpu_amdkfd_gfx_v8.c
amdgpu_amdkfd_gfx_v9.c
amdgpu_amdkfd_gfx_v10.c
amdgpu_amdkfd_gpuvm.c
amdgpu_atombios.c
amdgpu_atombios.h
amdgpu_atomfirmware.c
amdgpu_atomfirmware.h
amdgpu_atpx_handler.c
amdgpu_benchmark.c
amdgpu_bios.c
amdgpu_bo_list.c
amdgpu_bo_list.h
amdgpu_cgs.c
amdgpu_connectors.c
amdgpu_connectors.h
amdgpu_cs.c
amdgpu_csa.c
amdgpu_csa.h
amdgpu_ctx.c
amdgpu_ctx.h
amdgpu_debugfs.c
amdgpu_debugfs.h
amdgpu_device.c	drm/amdgpu: Enable DC support for Navi10	2019-06-22 09:34:07 -05:00
amdgpu_discovery.c
amdgpu_discovery.h
amdgpu_display.c
amdgpu_display.h
amdgpu_dma_buf.c
amdgpu_dma_buf.h
amdgpu_doorbell.h
amdgpu_dpm.c	drm/amdgpu: fix modprobe failure for uvd_4/5/6	2019-06-24 09:29:59 -05:00
amdgpu_dpm.h	drm/amd: add gfxoff support on navi10	2019-06-21 18:59:25 -05:00
amdgpu_drv.c	drm/amdgpu: add new navi10 DIDs	2019-06-21 18:59:33 -05:00
amdgpu_drv.h
amdgpu_encoders.c
amdgpu_fb.c
amdgpu_fence.c
amdgpu_gart.c
amdgpu_gart.h
amdgpu_gds.h
amdgpu_gem.c
amdgpu_gem.h
amdgpu_gfx.c	drm/amd: add gfxoff support on navi10	2019-06-21 18:59:25 -05:00
amdgpu_gfx.h
amdgpu_gmc.c
amdgpu_gmc.h
amdgpu_gtt_mgr.c
amdgpu_i2c.c
amdgpu_i2c.h
amdgpu_ib.c
amdgpu_ids.c
amdgpu_ids.h
amdgpu_ih.c
amdgpu_ih.h
amdgpu_ioc32.c
amdgpu_irq.c
amdgpu_irq.h
amdgpu_job.c
amdgpu_job.h
amdgpu_kms.c
amdgpu_mes.h	drm/amdgpu/mes10.1: add mes firmware info fields	2019-06-21 18:59:28 -05:00
amdgpu_mn.c
amdgpu_mn.h
amdgpu_mode.h
amdgpu_object.c
amdgpu_object.h
amdgpu_pll.c
amdgpu_pll.h
amdgpu_pm.c	drm/amd/powerplay: fix deadlock issue for smu_force_performance_level	2019-06-21 18:59:32 -05:00
amdgpu_pm.h
amdgpu_pmu.c
amdgpu_pmu.h
amdgpu_psp.c	drm/amdgpu/psp: add new psp interface for vcn updating sram	2019-06-21 18:59:33 -05:00
amdgpu_psp.h	drm/amdgpu/psp: add new psp interface for vcn updating sram	2019-06-21 18:59:33 -05:00
amdgpu_ras.c
amdgpu_ras.h
amdgpu_ring.c
amdgpu_ring.h
amdgpu_rlc.c
amdgpu_rlc.h
amdgpu_sa.c
amdgpu_sched.c
amdgpu_sched.h
amdgpu_sdma.c
amdgpu_sdma.h
amdgpu_socbb.h	drm/amd/display: use fixed-width data type for soc bounding box struct	2019-06-21 18:59:34 -05:00
amdgpu_sync.c
amdgpu_sync.h
amdgpu_test.c
amdgpu_trace.h
amdgpu_trace_points.c
amdgpu_ttm.c
amdgpu_ttm.h
amdgpu_ucode.c
amdgpu_ucode.h	drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h	2019-06-21 18:59:34 -05:00
amdgpu_uvd.c
amdgpu_uvd.h
amdgpu_vce.c
amdgpu_vce.h
amdgpu_vcn.c	drm/amdgpu/VCN: enable indirect DPG SRAM mode	2019-06-21 18:59:33 -05:00
amdgpu_vcn.h	drm/amdgpu/VCN: implement indirect DPG SRAM mode	2019-06-21 18:59:33 -05:00
amdgpu_vf_error.c
amdgpu_vf_error.h
amdgpu_virt.c
amdgpu_virt.h
amdgpu_vm.c
amdgpu_vm.h
amdgpu_vm_cpu.c
amdgpu_vm_sdma.c
amdgpu_vram_mgr.c
amdgpu_xgmi.c
amdgpu_xgmi.h
athub_v2_0.c
athub_v2_0.h
atom.c
atom.h
atombios_crtc.c
atombios_crtc.h
atombios_dp.c
atombios_dp.h
atombios_encoders.c
atombios_encoders.h
atombios_i2c.c
atombios_i2c.h
cik.c
cik.h
cik_dpm.h
cik_ih.c
cik_ih.h
cik_sdma.c
cik_sdma.h
cikd.h
clearstate_ci.h
clearstate_defs.h
clearstate_gfx9.h
clearstate_gfx10.h
clearstate_si.h
clearstate_vi.h
cz_ih.c
cz_ih.h
dce_v6_0.c
dce_v6_0.h
dce_v8_0.c
dce_v8_0.h
dce_v10_0.c
dce_v10_0.h
dce_v11_0.c
dce_v11_0.h
dce_virtual.c
dce_virtual.h
df_v1_7.c	drm/amdgpu: add sw_init to df_v1_7	2019-06-22 09:34:14 -05:00
df_v1_7.h
df_v3_6.c
df_v3_6.h
emu_soc.c
gfx_v6_0.c
gfx_v6_0.h
gfx_v7_0.c
gfx_v7_0.h
gfx_v8_0.c
gfx_v8_0.h
gfx_v9_0.c
gfx_v9_0.h
gfx_v10_0.c	drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)	2019-06-21 18:59:33 -05:00
gfx_v10_0.h
gfxhub_v1_0.c
gfxhub_v1_0.h
gfxhub_v1_1.c
gfxhub_v1_1.h
gfxhub_v2_0.c	drm/amd: the data retured from PRT is expected to be 0	2019-06-21 18:59:32 -05:00
gfxhub_v2_0.h
gmc_v6_0.c
gmc_v6_0.h
gmc_v7_0.c
gmc_v7_0.h
gmc_v8_0.c
gmc_v8_0.h
gmc_v9_0.c
gmc_v9_0.h
gmc_v10_0.c
gmc_v10_0.h
iceland_ih.c
iceland_ih.h
iceland_sdma_pkt_open.h
Kconfig
kv_dpm.c
kv_dpm.h
kv_smc.c
Makefile
mes_v10_1.c	drm/amdgpu/mes10.1: enable mes FW backdoor loading	2019-06-21 18:59:28 -05:00
mes_v10_1.h
mmhub_v1_0.c
mmhub_v1_0.h
mmhub_v2_0.c	drm/amd: the data retured from PRT is expected to be 0	2019-06-21 18:59:32 -05:00
mmhub_v2_0.h
mmsch_v1_0.h
mxgpu_ai.c
mxgpu_ai.h
mxgpu_vi.c
mxgpu_vi.h
navi10_ih.c
navi10_ih.h
navi10_reg_init.c	drm/amdgpu: initialize THM & CLK IP registers base address	2019-06-21 18:59:33 -05:00
navi10_sdma_pkt_open.h
nbio_v2_3.c
nbio_v2_3.h
nbio_v6_1.c
nbio_v6_1.h
nbio_v7_0.c
nbio_v7_0.h
nbio_v7_4.c
nbio_v7_4.h
nv.c	drm/amdgpu: Enable DC support for Navi10	2019-06-22 09:34:07 -05:00
nv.h
nvd.h
ObjectID.h
ppsmc.h
psp_gfx_if.h	drm/amdgpu/psp: add new VCN RAM ucode id to psp	2019-06-21 18:59:32 -05:00
psp_v3_1.c
psp_v3_1.h
psp_v10_0.c
psp_v10_0.h
psp_v11_0.c
psp_v11_0.h
r600_dpm.h
sdma_v2_4.c
sdma_v2_4.h
sdma_v3_0.c
sdma_v3_0.h
sdma_v4_0.c
sdma_v4_0.h
sdma_v5_0.c	drm/amdgpu/sdma5: incorrect variable type for gpu address	2019-06-21 18:59:27 -05:00
sdma_v5_0.h
si.c
si.h
si_dma.c
si_dma.h
si_dpm.c
si_dpm.h
si_enums.h
si_ih.c
si_ih.h
si_smc.c
sid.h
sislands_smc.h
soc15.c
soc15.h
soc15_common.h
soc15d.h
ta_ras_if.h
ta_xgmi_if.h
tonga_ih.c
tonga_ih.h
tonga_sdma_pkt_open.h
uvd_v4_2.c
uvd_v4_2.h
uvd_v5_0.c
uvd_v5_0.h
uvd_v6_0.c
uvd_v6_0.h
uvd_v7_0.c
uvd_v7_0.h
vce_v2_0.c
vce_v2_0.h
vce_v3_0.c
vce_v3_0.h
vce_v4_0.c
vce_v4_0.h
vcn_v1_0.c
vcn_v1_0.h
vcn_v2_0.c	drm/amdgpu/VCN: implement indirect DPG SRAM mode	2019-06-21 18:59:33 -05:00
vcn_v2_0.h
vega10_ih.c
vega10_ih.h
vega10_reg_init.c
vega10_sdma_pkt_open.h
vega20_reg_init.c
vi.c
vi.h
vi_dpm.h
vid.h