Evan Quan 82cac71c1b drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init ... That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-09-17 17:46:20 -04:00
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vega12
amd_powerplay.h
amdgpu_dpm.h
amdgpu_pm.h
amdgpu_smu.h	drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init	2020-09-17 17:46:20 -04:00
arcturus_ppsmc.h
cz_ppsmc.h
fiji_ppsmc.h
hardwaremanager.h
hwmgr.h
polaris10_pwrvirus.h
power_state.h
pp_debug.h
pp_endian.h
pp_thermal.h
ppinterrupt.h
rv_ppsmc.h
smu7.h
smu7_common.h
smu7_discrete.h
smu7_fusion.h
smu7_ppsmc.h
smu8.h
smu8_fusion.h
smu9.h
smu9_driver_if.h
smu10.h
smu10_driver_if.h
smu11_driver_if.h
smu11_driver_if_arcturus.h
smu11_driver_if_navi10.h
smu11_driver_if_sienna_cichlid.h	drm/amd/pm: update driver if file for sienna cichlid	2020-09-15 17:52:39 -04:00
smu12_driver_if.h
smu71.h
smu71_discrete.h
smu72.h
smu72_discrete.h
smu73.h
smu73_discrete.h
smu74.h
smu74_discrete.h
smu75.h
smu75_discrete.h
smu_types.h
smu_ucode_xfer_cz.h
smu_ucode_xfer_vi.h
smu_v11_0.h	drm/amd/pm: update driver if version for navy_flounder	2020-09-15 17:52:39 -04:00
smu_v11_0_7_ppsmc.h
smu_v11_0_7_pptable.h
smu_v11_0_ppsmc.h
smu_v11_0_pptable.h
smu_v12_0.h
smu_v12_0_ppsmc.h
smumgr.h
tonga_ppsmc.h
vega10_ppsmc.h
vega12_ppsmc.h
vega20_ppsmc.h