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https://github.com/Fishwaldo/Star64_linux.git
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775f1f7eac
Add defconfig and DTS for a virt board. Defconfig enables PCIe host and a number of virtio devices. DTS routes legacy PCI IRQs to the first four level-triggered external IRQ lines. CPU core with edge-triggered IRQs among the first four may need a custom DTS to work correctly. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
72 lines
1.5 KiB
Text
72 lines
1.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/ {
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compatible = "cdns,xtensa-iss";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "console=ttyS0,115200n8 debug";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x80000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "cdns,xtensa-cpu";
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reg = <0>;
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clocks = <&osc>;
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};
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};
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clocks {
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osc: osc {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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};
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};
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pic: pic {
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compatible = "cdns,xtensa-pic";
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/* one cell: internal irq number,
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* two cells: second cell == 0: internal irq number
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* second cell == 1: external irq number
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*/
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pci {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <0x1>;
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bus-range = <0x0 0x3f>;
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reg = <0xc0000000 0x04000000>;
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// BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
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ranges = <0x01000000 0x0 0xc4000000 0xc4000000 0x0 0x04000000>,
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<0x02000000 0x0 0xc8000000 0xc8000000 0x0 0x18000000>;
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// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
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interrupt-map = <
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0x0000 0x0 0x0 0x1 &pic 0x0 0x1
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0x0800 0x0 0x0 0x1 &pic 0x1 0x1
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0x1000 0x0 0x0 0x1 &pic 0x2 0x1
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0x1800 0x0 0x0 0x1 &pic 0x3 0x1
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>;
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interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
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};
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};
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