Guchun Chen d7b1ed4ac3 drm/amdgpu: add pcie bif ras related registers ... These registers will be accessed for querying ras errors. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-09-16 10:09:37 -05:00
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asic_reg	drm/amdgpu: add pcie bif ras related registers	2019-09-16 10:09:37 -05:00
ivsrcid	drm/amdgpu: add nbif v7_4 irq source header for vega20	2019-09-13 17:11:04 -05:00
amd_acpi.h
amd_pcie.h
amd_pcie_helpers.h
amd_shared.h	drm/amdgpu/display: add flag for multi-display mclk switching	2019-08-23 11:33:00 -05:00
arct_ip_offset.h	drm/amd/include: adjust base offset of SMUIO and THM for Arcturus	2019-07-30 23:48:34 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h
atomfirmware.h	drm/amd/powerplay: add smcdpminfo table v4_6 support	2019-07-30 23:48:33 -05:00
atomfirmwareid.h
cgs_common.h
cik_structs.h
discovery.h
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h
kgd_pp_interface.h	drm/amd/powerplay: Add interface to lock SMU HW I2C.	2019-08-27 08:17:42 -05:00
navi10_enum.h
navi10_ip_offset.h
navi12_ip_offset.h	drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'	2019-08-21 22:16:55 -05:00
navi14_ip_offset.h
pptable.h
renoir_ip_offset.h	drm/amd/display: update renoir_ip_offset.h	2019-09-13 17:49:25 -05:00
soc15_hw_ip.h
soc15_ih_clientid.h
v9_structs.h	drm/amdkfd: Extend CU mask to 8 SEs (v3)	2019-08-02 10:19:11 -05:00
v10_structs.h
vega10_enum.h	drm/amdgpu: Support new arcturus mtype	2019-09-13 17:35:48 -05:00
vega10_ip_offset.h
vega20_ip_offset.h
vi_structs.h