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ed3e4c6d3c
Newest devices have a new firmware load mechanism. This mechanism is called the context info. It means that the driver doesn't need to load the sections of the firmware. The driver rather prepares a place in DRAM, with pointers to the relevant sections of the firmware, and the firmware loads itself. At the end of the process, the firmware sends the ALIVE interrupt. This is different from the previous scheme in which the driver expected the FH_TX interrupt after each section being transferred over the DMA. In order to support this new flow, we enabled all the interrupts. This broke the assumption that we have in the code that the RF-Kill interrupt can't interrupt the firmware load flow. Change the context info flow to enable only the ALIVE interrupt, and re-enable all the other interrupts only after the firmware is alive. Then, we won't see the RF-Kill interrupt until then. Getting the RF-Kill interrupt while loading the firmware made us kill the firmware while it is loading and we ended up dumping garbage instead of the firmware state. Re-enable the ALIVE | RX interrupts from the ISR when we get the ALIVE interrupt to be able to get the RX interrupt that comes immediately afterwards for the ALIVE notification. This is needed for non MSI-X only. Cc: stable@vger.kernel.org Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
254 lines
8 KiB
C
254 lines
8 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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#include "iwl-context-info.h"
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#include "internal.h"
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#include "iwl-prph.h"
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void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
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{
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i;
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if (!dram->paging) {
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WARN_ON(dram->paging_cnt);
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return;
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}
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/* free paging*/
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for (i = 0; i < dram->paging_cnt; i++)
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dma_free_coherent(trans->dev, dram->paging[i].size,
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dram->paging[i].block,
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dram->paging[i].physical);
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kfree(dram->paging);
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dram->paging_cnt = 0;
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dram->paging = NULL;
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}
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int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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const struct fw_img *fw,
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struct iwl_context_info_dram *ctxt_dram)
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{
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i, ret, lmac_cnt, umac_cnt, paging_cnt;
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if (WARN(dram->paging,
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"paging shouldn't already be initialized (%d pages)\n",
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dram->paging_cnt))
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iwl_pcie_ctxt_info_free_paging(trans);
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lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
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/* add 1 due to separator */
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umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
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/* add 2 due to separators */
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paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
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dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
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if (!dram->fw)
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return -ENOMEM;
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dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
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if (!dram->paging)
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return -ENOMEM;
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/* initialize lmac sections */
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for (i = 0; i < lmac_cnt; i++) {
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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ctxt_dram->lmac_img[i] =
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cpu_to_le64(dram->fw[dram->fw_cnt].physical);
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dram->fw_cnt++;
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}
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/* initialize umac sections */
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for (i = 0; i < umac_cnt; i++) {
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/* access FW with +1 to make up for lmac separator */
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ret = iwl_pcie_ctxt_info_alloc_dma(trans,
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&fw->sec[dram->fw_cnt + 1],
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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ctxt_dram->umac_img[i] =
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cpu_to_le64(dram->fw[dram->fw_cnt].physical);
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dram->fw_cnt++;
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}
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/*
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* Initialize paging.
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* Paging memory isn't stored in dram->fw as the umac and lmac - it is
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* stored separately.
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* This is since the timing of its release is different -
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* while fw memory can be released on alive, the paging memory can be
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* freed only when the device goes down.
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* Given that, the logic here in accessing the fw image is a bit
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* different - fw_cnt isn't changing so loop counter is added to it.
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*/
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for (i = 0; i < paging_cnt; i++) {
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/* access FW with +2 to make up for lmac & umac separators */
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int fw_idx = dram->fw_cnt + i + 2;
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
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&dram->paging[i]);
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if (ret)
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return ret;
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ctxt_dram->virtual_img[i] =
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cpu_to_le64(dram->paging[i].physical);
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dram->paging_cnt++;
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}
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return 0;
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}
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int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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const struct fw_img *fw)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_context_info *ctxt_info;
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struct iwl_context_info_rbd_cfg *rx_cfg;
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u32 control_flags = 0, rb_size;
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int ret;
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ctxt_info = dma_alloc_coherent(trans->dev, sizeof(*ctxt_info),
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&trans_pcie->ctxt_info_dma_addr,
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GFP_KERNEL);
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if (!ctxt_info)
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return -ENOMEM;
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ctxt_info->version.version = 0;
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ctxt_info->version.mac_id =
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cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
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/* size is in DWs */
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ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
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switch (trans_pcie->rx_buf_size) {
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case IWL_AMSDU_2K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
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break;
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case IWL_AMSDU_4K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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break;
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case IWL_AMSDU_8K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
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break;
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case IWL_AMSDU_12K:
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rb_size = IWL_CTXT_INFO_RB_SIZE_12K;
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break;
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default:
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WARN_ON(1);
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rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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}
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BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
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control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG |
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(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
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IWL_CTXT_INFO_RB_CB_SIZE_POS) |
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(rb_size << IWL_CTXT_INFO_RB_SIZE_POS);
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ctxt_info->control.control_flags = cpu_to_le32(control_flags);
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/* initialize RX default queue */
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rx_cfg = &ctxt_info->rbd_cfg;
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rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
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rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
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rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
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/* initialize TX command queue */
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ctxt_info->hcmd_cfg.cmd_queue_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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ctxt_info->hcmd_cfg.cmd_queue_size =
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TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
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if (ret) {
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
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ctxt_info, trans_pcie->ctxt_info_dma_addr);
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return ret;
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}
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trans_pcie->ctxt_info = ctxt_info;
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iwl_enable_fw_load_int_ctx_info(trans);
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/* Configure debug, if exists */
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if (iwl_pcie_dbg_on(trans))
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iwl_pcie_apply_destination(trans);
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/* kick FW self load */
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iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
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iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
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/* Context info will be released upon alive or failure to get one */
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return 0;
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}
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void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!trans_pcie->ctxt_info)
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return;
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
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trans_pcie->ctxt_info,
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trans_pcie->ctxt_info_dma_addr);
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trans_pcie->ctxt_info_dma_addr = 0;
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trans_pcie->ctxt_info = NULL;
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iwl_pcie_ctxt_info_free_fw_img(trans);
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}
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